during verifying power-up conditions I observed some strange behavior.
During power supply sequencing, there can be seen some relation between povering Vcc (0V9) and 1V8 used for IO.
When 0V9 is powered on, it starts slowly charging 1V8 rail that is tri-stated at the time. Using PMIC I tried to delay powering other power supplies in the same group as 0V9 and the charging really starts with 0V9. Only FPGA runs from 0V9 and there seems to be no external conection between 0V9 and 1V8.
Is this some internal leakage inside FPGA? I understand that idelally, ramp-up shall be monotonous, could this be a source of any problems related to POR (or other circuitry in FPGA)?
Scope snapshot attached.
There is a tRAMP time specified in the datasheet, within which all the power supplies should be up. Also there are some power-up sequencing considerations for the device. Please check the whole section of Power Management in GPIO handbook.