Design with multiple PMA/PCS cores

[supermant]

Hi,

I am trying to have a design which is connected as shown in the image.

As per my understanding the 4 PHY(PMA/PCS) blocks would typically be in 4 different clock domains.
What would be the best way to clock the design, in order to reduce latency? If necessary I can use one of the PMA/PCS clocks as the system clock for the design. But then how do I do the CDC for the other 3?

Thanks in advance

[Ash_R_Intel]

Hi,

Usually every transceiver block has its own clocking structure which includes a PLL. Please check the corresponding transceiver user guide for more details.

In devices like Stratix 10 and below, you can also use the transceiver PLL generated clock for the FPGA fabric design as well.

Regards