CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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I am wondering what is the delay for a AND (OR,NOT) gate in latest ASIC technology? and what about a typical flip-flop? The reason I ask is I want to calculate the delay of my digital design by hand, thanks.
If you are dealing with fpga then there are no gates as you see in RTL code. Code or schematic is mapped to LUTs/registers and dedicated DSP blocks. It might be best to check timing simulation model to tell you what you want.
