multiplier delay of embedded multiplier

[Altera_Forum]

Hi, 

 I am designing an custom hardware and it requires multipliers, so since there are embedded multipliers available in cyclone II, I decided to use them by using the the multiply symbol in my vhdl code.(mentioned in alter manual). Now the doubt I had is what would be the time for this multiplication, so based on this I can implement my FSM. I am using a 16x16 signed multiplication and the clock frequency is 50 MHz. The board I am using is EP2C35F672C6 in the cyclone II family. So how do i find the latency time for this multiplier.  Please help.  Thanks, Joseph

[Altera_Forum]

Synthesis will do the same latency as your RTL. So if you don't have any registers, it will be purely combinatorial. If you have one at the end, it will probably suck that one into the embedded block. With your HDL open in Quartus II, go to Edit -> Insert Template -> VHDL/Verilog and there should be some good multiplier examples.

[Altera_Forum]

Hi Rysc, 

 Thanks for your prompt reply. When i was going through the Nios II Core Implementation document, it is mentioned that for the Nios II/f core, the embedded multiplier can be included for multiplication and the cycles for the mul/muli instruction which used the embedded multiplier is 5 cycles for 32x16 multiplication, so i was thinking that the 16x16 might also take more than one cycle or the combinatorial delay could be more than 20 ns (1/50Mhz the clock freq of the SoC). Any idea on this?  Thanks, Joseph

[Altera_Forum]

Nios does it's own thing, and if the RTL has five levels of registers, then it will take that long. The actual embedded multiplier doesn't have 5 pipeline registers in it, so some of those will be for other logic(look at the Cyclone II handbook to see what is really built into the block). Synthesis must always match your code, the key is trying to write code that takes advantage of what's in the hardware. As long as you're inferring the blocks, you should be good.

[Altera_Forum]

We need to separate the idea of registers in RTL and those inside mult block. 

If you infer with * symbol then you can only add register on input or output but not inside. if you use megawizard you can additionally add registers inside as well as on inputs/outputs.   As far as I know you cannot infer internal pipe and I think it defaults to none.

[Altera_Forum]

--- Quote Start ---  As far as I know you cannot infer internal pipe and I think it defaults to none.  --- Quote End ---    IIRC I think it was decided that you can infer internal registers by putting the extra registers on the input to the multiply (with one for output) and turning on register retiming.  I havent checked this though.

[Altera_Forum]

Cyclone II doesn't have an internal pipe. I think on Stratix devices the "internal pipe" is between the multiplier and the adder, but not inside. The one I would be curious about is building the wider mults, like a 36x36 or 54x54, which stitches together the smaller mult units. I'm sure there's a way to do this, but not sure how easily it is inferred. At some point the arithmetic is best done with the megawizard to get a controlled implementation. For example, I had a case of a simple multiplier where I didn't need the adder(this was Stratix IV). Synthesis kept putting the output register after the bypassed adder, where I needed it before the adder(or vice versa, I can't remember). I ended up having to use the megawizard to craft the implementation to meet timing.

[Altera_Forum]

Yeah, 

 When i was exlporing the option of adding the multiplier using the megawizard it throws out the option asking for pipeling, latency etc.... but what i wanted to know is that if I just put a multiply symbol ( *) in my vhdl code, i read in the altera documentation that the embedded multiplier is instantiated without any pipelining, but since it is 16x16 multiplication ( which is formed by joining the small blocks like 9x9), will this combinational circuit have a delay of more than a clock cycle in my case 20 ns.  Thanks, Joseph

[Altera_Forum]

somewhat offtopic, but the V families are supposed to support HDL inferring of (almost) all DSP block modes. i imagine this will include internal pipelines

[Altera_Forum]

--- Quote Start ---  Yeah,  When i was exlporing the option of adding the multiplier using the megawizard it throws out the option asking for pipeling, latency etc.... but what i wanted to know is that if I just put a multiply symbol ( *) in my vhdl code, i read in the altera documentation that the embedded multiplier is instantiated without any pipelining, but since it is 16x16 multiplication ( which is formed by joining the small blocks like 9x9), will this combinational circuit have a delay of more than a clock cycle in my case 20 ns.  Thanks, Joseph  --- Quote End ---    zero pipeline means no delay of registering. You expect output to be ready but delayed only "through combinatorial logic" which should be well below your clock period otherwise the design will fail badly from logic delays.