I have downloaded the .par file from the link (https://fpgacloud.intel.com/devstore/platform/16.0.0/Standard/nios-ii-simple-socket-server-ethernet-...) and followed the steps to create software project as given in the pdf https://www.altera.com/en_US/pdfs/literature/tt/tt_nios2_tcpip.pdf .
The quartus version that I've used is 17.1.
If I use Quartus version 16.0, I am getting the different errors related to "DESCRIPTOR_MEMORY_BASE" undeclared here (not in a function).
I am attaching the screenshots of the errors related to both versions i.e. 16.0 and 17.1.
I have even tried the fixes that are mentioned in https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/soluti...
wherein I have used eth_std_main_system.qsys as the QSYS_TOP mentioned in that link. But it couldn't reslove.
Kindly help me out
This issue seems like due to SGDMA to MSGDMA migration. Intel is recommending the MSGDMA. Please check this document:
https://www.altera.com/en_US/pdfs/literature/ug/ug_embedded_ip.pdf (page 297) First line. This change applied also to the TSE, the drivers expect to work with msgdma not sgdma.
Could you try to change from the sgdma to msgdma in your .qsys file?
For your information, there is an example for Nios II Simple Socket Server Ethernet in Quartus Prime Standard v17.1.1: https://fpgacloud.intel.com/devstore/platform/17.1std.1/Standard/nios-ii-simple-socket-server-ethern...,
Also, there is an forum community discuss about this problem, you can see the detail in link below:
I will try changing from the sgdma to msgdma in the .qsys file. The example for Nios II Simple Socket Server Ethernet in Quartus Prime Standard v17.1.1 is for the MAX 10 board. My exploration is limited to Cyclone GT V. Thank you for your reply.