Signaltap problem with Stratix 10 Production Kit

[SDe_J]

I have created a very simple project in Quartus 18.0 for a stratix 10 development kit. The project uses a 100MHz clock to drive a counter, which counts from 0 to 99. I have added a signaltap instance which uses the 100MHz clock and observes the counter.

During compilation of the project, I get these warnings:

Warning(332060): Node: altera_reserved_tck was determined to be a clock but was found without an associated clock assignment.     This warning appears six times: (For each temperature/speed model I assume)     Warning(332182): No path is found satisfying assignment "set_max_skew -from [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_auto_signaltap_0|sld_signaltap_inst|sld_signaltap_body|sld_signaltap_body|intel_stp_status_bits_cdc_u1|stp_status_bits_in_reg[*]}] -to [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_auto_signaltap_0|sld_signaltap_inst|sld_signaltap_body|sld_signaltap_body|intel_stp_status_bits_cdc_u1|stp_status_bits_out[*]}] 1.000 ". This assignment will be ignored.

The compilation completes with no errors, so I go to signaltap to program the board. After choosing the correct device and .sof file, I click the program button.

During programming, this message appears in the System tab of the Quartus message pane:

Info(209060): Started Programmer operation at Fri Feb 1 15:23:52 2019   Info(18942): Configuring device index 1   Info(18943): Configuration succeeded at device index 1   Info(209011): Successfully performed operation(s)   Info(209061): Ended Programmer operation at Fri Feb 1 15:23:53 2019

Despite this seemingly successful programming, the signaltap status bar still says 'Program the device to continue' with a red background. If I try to acquire data, This message appears in the System tab of Quartus:

Error(261005): Can't find the instance. Download a design with SRAM Object File containing this instance.

I believe the issue has something to do with the warning above (No path is found satisfying assignment....). I tried investigating this using the Timing Analyser.

I opened Timing analyser, and ran the 'Create Timing Netlist' command. After that I ran

get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_auto_signaltap_0|sld_signaltap_inst|sld_signaltap_body|sld_signaltap_body|intel_stp_status_bits_cdc_u1|stp_status_bits_in_reg[*]}

Which did not produce any errors. Somehow this register is not defined during programming, but when I run 'create timing netlist'.

In fact, running the whole command

set_max_skew -from [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_auto_signaltap_0|sld_signaltap_inst|sld_signaltap_body|sld_signaltap_body|intel_stp_status_bits_cdc_u1|stp_status_bits_in_reg[*]}] -to [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_auto_signaltap_0|sld_signaltap_inst|sld_signaltap_body|sld_signaltap_body|intel_stp_status_bits_cdc_u1|stp_status_bits_out[*]}] 1.000

produces no errors.

Why would this cause an error at compile time, but not when running the timing analser?

I have tried this in both Quartus 18.0 and 18.1. In 18.1, I get this error when I try to program the board:

Info(209060): Started Programmer operation at Fri Feb 1 15:49:42 2019   Info(18942): Configuring device index 1   Error(18948): Error message received from device: Detected hardware access error. There is a failure in accessing external hardware. (Subcode 0x0032, Info 0x00000000, Location 0x0000C400)   Error(20072): A PMBUS error has occurred during configuration. Potential errors: Incorrect VID setting in Quartus Project. The target device fails to communicate to smart regulator or PMBUS Master on board.   Info(209028): Operation canceled   Info(209061): Ended Programmer operation at Fri Feb 1 15:49:44 2019

I suspect my power settings and VID are incorrect, but I'm not sure why this would be a problem in Quartus 18.1, but not 18.0.

Any help would be very appreciated

Thanks,

-Sam

[sstrell]

First, did you enable Signal Tap (the .stp file) for the design? Check the Signal Tap category in the project settings to make sure you enabled it (and recompile once enabled). If you created the file and then didn't enable it, it won't work. Are you manually adding an instance of Signal Tap to your HDL code or simply using the .stp file (preferred method)? The warning you see is not the issue. You don't normally need to add timing constraints for the JTAG interface or Signal Tap. Remove those constraints you added.

As for the SmartVID errors, I don't believe the S10 on the dev kit is set up for SmartVID. So perhaps your project is targeting the wrong device. My H-tile board projects target 1SG280HU2F50E2VGS1 (replace H with L for an L-tile, I think).

The easiest way to make sure you set up a project correctly for a dev kit is to either use a downloaded example project for the board or choose the Board tab when you're going through the New Project Wizard.

[SDe_J]

Hi sstrell,

I have ensured that the signaltap file is enabled (if I disable it, I don't get the compile warnings about signaltap that I posted). I have not added any timing constraints to the design, but those warnings show up anyway.

I got the device I'm using from an example project for the stratix 10. The precompiled .sof file for that project downloads to the board correctly, so I'm reasonably certain that I've got the device correct.

-Sam

[sstrell]

I guess at this point, you should trash the db folder and recompile the whole project. Something is not matching up and a full recompile might fix it.

[SDe_J]

There's no db folder, but there is a qdb file. I've deleted that and the signaltap file, but still get the same result when I compile and program the board.

[sstrell]

Sorry, I was thinking of the Standard edition. Yes, trashing the qdb folder and recompiling is what I meant. So if you do that and disable the .stp file in the settings, it still doesn't work?

[SDe_J]

Yes, deleting the qdb folder and recompilling produces the same results.

[SreekumarR_G_Intel]

Hello there, “ Altera_reserved_tck was determined to be a clock but was found without an associated clock assignment. “ Since the Quartus tool identified you are using it for clock but didn’t provide the SDC constraint. Why would this cause an error at compile time, but not when running the timing analser? Quartus tool know in your design you have clock , but it is just giving warning you didn’t included the SDC. Can I assume after the providing the timing info , you can able use the signal tap analyzer with 18.0 ? Sorry if I misunderstood. I really wonder :(. About Quartus pro version there is work around, Can you check below link , i think error message is more related to what you facing ? https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/component/2017/error-18948---error-message-received-from-device--detected-inval.html Thank you , Regards, Sree

[SDe_J]

I tried the suggestion in the link (setting SW1 to [11]), but it produced no change in my problem.

I am still unable to use signaltap in either 18.0 or 18.1. Do I need to provide timing constraints for signaltap? If so, how do I do this? I'm not currently providing any constraints on the project. My project has no .sdc file, but I get the warnings shown in my original post.

[SDe_J]

I added a constraint for altera_reserved_tck:

create_clock -period "41.667 ns" -name {altera_reserved_tck} {altera_reserved_tck}

Now I no longer get the warnings about

Warning(332182): No path is found satisfying assignment "set_max_skew -from [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_auto_signaltap_0|sld_signaltap_inst|sld_signaltap_body|sld_signaltap_body|intel_stp_status_bits_cdc_u1|stp_status_bits_in_reg[*]}] -to [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_auto_signaltap_0|sld_signaltap_inst|sld_signaltap_body|sld_signaltap_body|intel_stp_status_bits_cdc_u1|stp_status_bits_out[*]}] 1.000 ". This assignment will be ignored.

Which is an improvement, but signaltap still doesn't work....

[SreekumarR_G_Intel]

Are you using Startix 10 GX L tile Development kit ? If your design is not confidential, Can you attach in the forum so i can have a look ?

I really dont think so there is link for signal tap analyser not working because of not including or including the timing constraint.

Thank you ,

Regards,

Sree

[SDe_J]

Hi Sree,

You are correct, I am using the Stratix 10 GX L-tile dev kit. Attached is a qar file containing my project. I am currently using Quartus 18.0.

If you are able to take a look and see if you spot anything obvious, that would be great.

Thanks,

-Sam

[SreekumarR_G_Intel]

hello Jong, Sorry , I caught into lot of other issue and took my all time ....Can i kindly know you still facing the issue .if yes I will look at. I just got the S10 L time dev kit as well. Thank you , Regards, Sree

[Salma_M_Intel]

What was the solution to this? I am finding that I run into the same error when I plug in the QSFP cables into my Stratix10 MX Dev Kit.

[SreekumarR_G_Intel]

Can you kindly paste the error message again here ?

Thank you,

Regards,

Sree