race condition in sim. Can I use Transport delay?

[Altera_Forum]

Hi All, 

 In my RTL, I am going from a 1x clock to 2x clock, both are synchronous and pos-edge aligned, both from same PLL. However the 2x clock is through an Altera Clock Control mux (Alt_ClkCtrl megafunction).   I see a race condition on a signal which is going from 1x to 2x clock and I suspect it is due to Simulator's delta time, as the signal is assigned in a process using 1x clock, while it is then used in a process using 2x clock.  I am sure in HW (on the FPGA) this will not happen, as the propagation delay between the two flops will greater than the skew between the clocks.   So to 'fix' this problem can I use a transport delay on this signal. The race won't happen then.  Is it this a good practice or there is a better method to fix this race condition.  Thanks

[Altera_Forum]

--- Quote Start ---  Hi All,  In my RTL, I am going from a 1x clock to 2x clock, both are synchronous and pos-edge aligned, both from same PLL. However the 2x clock is through an Altera Clock Control mux (Alt_ClkCtrl megafunction).   I see a race condition on a signal which is going from 1x to 2x clock and I suspect it is due to Simulator's delta time, as the signal is assigned in a process using 1x clock, while it is then used in a process using 2x clock.  I am sure in HW (on the FPGA) this will not happen, as the propagation delay between the two flops will greater than the skew between the clocks.   So to 'fix' this problem can I use a transport delay on this signal. The race won't happen then.  Is it this a good practice or there is a better method to fix this race condition.  Thanks  --- Quote End ---    Hi,  I think you can use a tranport delay for the RTL simulation. For your FPGA implementation Quartus will try to solve this issue for you, but you have to set the right constrains.  Kind regards  GPK