receive 256 bits data from PS via axi lite slave Message contains an image

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

receive 256 bits data from PS via axi lite slave Message contains an image

1,046 Views

Hey evryone !

I'm really stuck for a few days!

I am sending 256 bits looped from my PS. But I think that I get juste the last 4 bytes of 8*4 that i send !

What I want from you is a few vhdl code line that allow me to receive all of my data (8 * 32 bits).

You will find enclosed a photo of the result that I get and the vhdl code axi generated by vivado

Waiting for your reply. thank you

https://alteraforum.com/forum/attachment.php?attachmentid=13870&stc=1

https://alteraforum.com/forum/attachment.php?attachmentid=13869&stc=1

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.