I am using stratix 10 development kit,
From transceiver user guide:
A.4.7. Embedded Streamer (Native PHY) and
A.1.4. Embedded Streamer (ATX PLL)
Shares common register space for embedded streamer. for changing profile.
And PreSICE have common register space.
So do they have common register space for other configurations too ? like loopback mode change.
In my project i have to use dynamic reconfiguration for both ATX PLL and PHY.
as it is READ MODIFIED WRITE, with respect to which avmm_wait_request i can access the register data !
I am confused over its architecture,
1) same AVMM bus can be connected to ATX PLL and NATIVE PHY ?
2) to modify loopback modes Native PHY,AVMM Bus should be different,
for any change in ATX PLL different AVMM BUS ?
Please see the attached snapshot, and share which architecture is correct
hope i will get clarity over this.
As I understand it, this case seems to be similar to another which was addressed. Please feel free to let me know if this inquiry is something different. Thank you.
I believe the initial inquiry has been addressed in another thread. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.