reset MAX II

[Altera_Forum]

hi, 

i would like to know if i can rely on the power-on-reset of MAX II to know the initial values of the outputs? or should i use external reset?   thanks sharen

[Altera_Forum]

This issue was discussed in heated recent threads.  

 In short, no it is unreliable but yes it is, provided you exercise some care.   The power-up values themselves are reliable(provided you set its Don't care off) since async reset is applied soon after configuration phase.   The problem is that it is released non-synchronised to clk(or clks) and hence may upset your design at startup. To overcome that generate your own internal reset(depending on powerup values being 0 e.g. a counter), then apply it as usual to async ports (after being synchronised to its clk)

[Altera_Forum]

--- Quote Start ---  This issue was discussed in heated recent threads.    In short, no it is unreliable but yes it is, provided you exercise some care.   The power-up values themselves are reliable(provided you set its Don't care off) since async reset is applied soon after configuration phase.   The problem is that it is released non-synchronised to clk(or clks) and hence may upset your design at startup. To overcome that generate your own internal reset(depending on powerup values being 0 e.g. a counter), then apply it as usual to async ports (after being synchronised to its clk)  --- Quote End ---    So, if I understood you right, it sounds like it would be quite simple to use a two-flop reset synchronizer for this. I can have two flops with a initial state 0 and no reset pin. They should come up as zero. Then the fitst flop goes to the second one and the second one goes to the resets of all other flops. Then it resets asynchronously because of the CPLD`s internal mechansim and then come out synchronously with two clocks.  -G

[Altera_Forum]

Hello, sorry for question and for my bad english, i am a student, and I am doing a card whith EPM570, for drive a small 

step motor, I have to generated one pulse an direction, I have already done a part of program in VHDL, where I put in 2 location the maximum speed and the mimimum speed, and now, whith 2 buttons up and down, i  whant start my frequency which low speed and increase until arrive at maximum frequency, whith ramp on when i push button, and decrease whith ramp when I release the button, example, I start whith one duty cicle off 50 ms, for low speed, and in about 1 second to arrive to reduce the duty cycle until, the value off max frequency is equal to value in the location already done, and decrease when the button are released, I have used many system but do not work, can somebody send suggestion how I can do?? Thanks in advance regards Maurizio

[Altera_Forum]

A neat way is to use modulo adder(variable counter steps) as follows: 

 choose a free running binary accumulator (say for simplicity of discussion) that has capacity of 256 maximum. Increment it from zero by adding a step of your choice between 1 and 255 then use the overflow as your clock enable to control clock rate on whatever logic. if step = 1 then it gives overflow flag every 256 clocks. if step= 128 then it overflows every 2 clocks and so on. You will need another counter to generate the step of 1~255 that is enabled on the button.  To detect overflow flag add one extra bit to accumulator i.e. use 9 bits for our simple example. This 9th bit will give you directly one pulse whenever overflow occurs since the accumulator is binary limited to 255 and rolls over.  The clock enable rate for a step size (s) = s/2^8 * clock rate