reset input signal

[Altera_Forum]

Hi. I heard that the reset signal is better in active low. Is it true? If it is true may i know why? 

 thanks

[Altera_Forum]

Active-low signals are mainly a legacy from TTL days, I think. With weak-pullup resistors of Altera FPGAs (and other devices as well), they still make sense.

[Altera_Forum]

They do not make sense inside the FPGA though. I use then externally though. And anyway you have to synchronize any external signals so why not sync and invert ? That is what I do.

[Altera_Forum]

Hello, 

 I am not sure about this in altera, but Xilinx suggest for Virtex 6 to use active low control signals because the FF of their Logic Elements have active low signals, so if you use Active High control signal, your signal must cross one LUT to be inverted before connected, it depends of the architecture of the FPGA.  Good Luck.  DABG

[Altera_Forum]

That got me curious, so I checked the documentation: in Virtex6, CE and SR are active high.

[Altera_Forum]

AFAIK all altera and xilinx internal control signals are active high by default.

[Altera_Forum]

Most control signals in Altera devices have a programmable inversion (usually LAB wide). Then high or low active async clear shouldn't matter, and should not need any LUT negation. 

 I'm not sure about Xilinx, but I'd be surprised if it's not the same.

[Altera_Forum]

Hello, 

 In the next white paper you can confirm the info that I wrote.  http://www.xilinx.com/support/documentation/white_papers/wp248.pdf  "Active-High control signals should be used wherever possible in the HDL code or instantiated components"  About the use of a LUT for the inversion of the signals: "In certain situations, device utilization can decrease due to the use of a LUT as an inverter and the additional restrictions of register packing sometimes caused by active-Low control signals. Timing can also be affected by the use of active-Low control signals".   I saw this in a tutorial that I made 2 months ago, I confused between High and Low.  Good luck.  Bye.  DABG

[Altera_Forum]

--- Quote Start ---  http://www.xilinx.com/support/documentation/white_papers/wp248.pdf  "Active-High control signals should be used wherever possible in the HDL code or instantiated components"  --- Quote End ---    Interesting. But this applies to Xilinx devices, and only to Virtex-5 and later ones.  All Altera FPGA families have a programmable inversion for each one of the control signals. And it seems this was true for Xilinx as well, until Virtex-4. For some reason Xilinx decided to remove the programmable inversion feature on later devices.