restricted fmax

[Altera_Forum]

My design with a Stratix2GX130 is timing-clean (no findings in TimeQuest' "report top failing paths").  

The design is fully constrained, everything seems to be ok.  But when I look at the list of TimeQuest' "Report fmax summary" I see a column "Restricted fmax" with much lower values.  And there are notes like: -limit due to minimum period restriction (tmin) -limit due to high minimum pulse width violation (tch) -limit due to minimum port rate restriction (tmin) -limit due to minimum period restriction (max I/O toggle rate)  --> Are this serious warnings? --> where can I find some hints where these restrictions come from?  Thanks for any help!

[Altera_Forum]

Since you dont' have any failing paths, I assume your restricted fMax are still high enough to meet your constrains. 

Thus, no, it's not even a warning much less a serious one.  The fMax report just provides some ballpark numbers on how fast each clock in your design could be. But it's really just a ball park number. (unrestricted fMax just takes into account the register-to-register delays The restricted fMax takes into account some more things, such as max I/O toggle rates. And neither takes into account signal that cross clock domains, for example.

[Altera_Forum]

Those values are valid and should not be ignored. If you attempt to exceed the restricted Fmax then you will be operating the device outside of spec and you should not expect it to function properly.