running C without jtag

[Altera_Forum]

Hello, 

 I'm working on a module that is a part of a big project that's done on several stratix 3 FPGAs on a Gidel board. My problem is this:  In all the NIOS guides that I read I only see that the C code is being run/started from a GUI (NIOS IDE) which is activated via jtag/USB blaster or something like that. could someone refer me to a guide/reference that explains how to choose a C program and have it connected to the SOPC designer (or something like that) so that when I load the bitstream to the FPGA the code is already there.  Maybe I'm not explaining myself too well. What I mean is that the program will not need a jtag so that when the FPGA is loaded it will always work and only when some bit in the RTL is triggered it will start a method of the code.    Thanks, Ayal

[Altera_Forum]

Ayal, 

 There are any number of ways that this can be done. The simplest is probably just to point your Reset Address at a non-volatile memory (CFI flash or EPCS), program the flash, and then allow the processor to load the code from this non-volatile memory on boot/reset.  There are other methods mentioned in the Advanced Boot Copier AN (an-458 (http://http://www.altera.com/literature/an/an458.pdf)). It sounds like you'd be interested in this document.  Cheers,  - slacker

[Altera_Forum]

this tutorial uses on chip RAM which is the easiest way to include your Nios code in the FPGA config data: 

 http://www.altera.com/literature/tt/tt_nios2_hardware_tutorial.pdf  you can use a parallel I/O peripheral connected to the Nios to read bits from your RTL and make the code do certain functions based upon those bits.