scfifo-what is the problem

[Altera_Forum]

from this vhdl code,i make this as an avalon slave component on the cyclon2 device, and i get the output (sender) as peaks (nearly impulse) , what may be the problem? 

is it something related to lpm_showahead or use_eab values,or rdrequest and wrrequest timing?  library altera; use altera.altera_europa_support_lib.all;   library altera_mf; use altera_mf.all;  library lpm; use lpm.all;  library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;  entity tele is      port (  -- inputs:  signal address : in std_logic_vector (1 downto 0);  signal chipselect : in std_logic;  signal clk : in std_logic;  signal reset_n : in std_logic;  signal write_n : in std_logic;  signal writedata : in std_logic_vector (7 downto 0);    -- outputs:  --signal the_output : out std_logic;  signal tx_empty : out std_logic;   signal tx_full : out std_logic;  signal tx_used : out std_logic_vector (5 downto 0);  signal sender : out std_logic_vector (7 downto 0)  ); end entity tele;  architecture europa of tele is  component scfifo is  generic (  lpm_numwords : integer;  lpm_showahead : string;  lpm_width : integer;  lpm_widthu : integer;  overflow_checking : string;  underflow_checking : string;  use_eab : string  );  port (  signal full : out std_logic;  signal usedw : out std_logic_vector (5 downto 0);  signal q : out std_logic_vector (7 downto 0);  signal empty : out std_logic;  signal rdreq : in std_logic;  signal data : in std_logic_vector (7 downto 0);  signal sclr : in std_logic;  signal clock : in std_logic;  signal wrreq : in std_logic  );  end component scfifo;    signal wrrequest : std_logic;  signal rdrequest : std_logic;   signal sclr_me : std_logic;   begin  write_fifo : scfifo  generic map(  lpm_numwords => 64,  lpm_showahead => "off",  lpm_width => 8,  lpm_widthu => 6,  overflow_checking => "on",  underflow_checking => "on",  use_eab => "off"  )  port map(  clock => clk,  data => writedata,  empty => tx_empty,  full => tx_full,  q => sender,  rdreq => rdrequest,  sclr => sclr_me,  usedw => tx_used,  wrreq => wrrequest  );   rdrequest <='1';  sclr_me <= '0';  wrrequest <= '1';  end europa;

[Altera_Forum]

Hi, 

 There is no functional purpose in using a fifo if you write and read data together at the same rate.

[Altera_Forum]

yes,kaz that is right but here i m trying to see that the output of the fifo is electrically and logically right,i tried meaningful fifo usage also like : 

 process(clk,reset_n) begin  if reset_n=0 then  sender <="00000000"; elsif clk'event and clk='1' and full = '1' then sender_out <= sender; end if;  something like that but the result was same that i see the output pins' voltages very strange like impulses.  for example i write 0xa5 continuosuly,i look @ the pins of the output sender from oscilloscope and see the 1 bits and 0 bits @ right pins but 1 bits are electrically strange,that is they are not a step like function but like periodic impulses  is it something about the concurrency problem of the rdrequest and wrrequest signals?

[Altera_Forum]

Your last code still doesn't tell me about state of fifo rd/wr itself. 

However, you should avoid reading empty fifo at start or full fifo. you better use SignalTap to make your study instead of scope. go to files > new > stp(signaltap) > enter your clk in the clk entry and enter your nodes, recompile and see. it needs usb blaster connected.  I don't foresee any problems with altera scfifo. You better wait for few bytes then start reading.

[Altera_Forum]

thanx for attention kaz,yes,thats right that reading empty or full fifo is wrong,so i make the rdrequest high when usedw signal (how many words exist in buffer) is for example 8 or 9 for a 64 byte buffer,and in vwf file the simulation is ok but when i instantiate this vhdl code in sopc and create the system, i get those periodic impulses on oscilloscope instead of the 1 bits. 

i will also try to see the results in signaltap as you suggest.