EPM7128AE - strange FlipFlop behaviour

[Altera_Forum]

I use the scematic on EPM7128AE you'll see in schaltung.jpg. 

There is a pixelclock (signal 3) which should comes out of the JK-FlipFlop with half the frequency. This works fine but sometimes there is only a short puls out of the JK-FF and the signal flips back to old state. Line 2 should be a Puls on every edge. I'm sure that it's not a problem of the CLRN of the JK-FF.  Maybe it has to do with slew rates or something like this. I tried 'Slow Slew Rate' ON, but still the same problem.  I use Quartus II V8.1.  Daniel

[Altera_Forum]

If the device ois powered correctly, the reason for the observed behaviour is most likely a timing violation at the circuit inputs. But these signals are shown in the waveforms, I think. Trace 2 seems unrelated to the circuit? Or is it inPIX_CLOCK shown with an arbitrary delay? In this case, the relation to the input clock should be shown as well. 

 If trace 3 and 4 are recorded with correct delay, there's apparently a glitch causing the extra toggle. Although it's not fully visible in the waveform, it may be present internal to the CPLD. Most likely setup or hold timing of inPIX_CLOCK has been violated here.

[Altera_Forum]

Trace2 is related to Trace4 and the signal is generated inside the CPLD and comes out of a Pin of the device. 

Trace 3 and 4 are intern signals,which I temporarly routed to an outputpin to trace it with my scope (because I noticed the behaviour of Trace 2). I think there is a glitch or spike in front of the edge of Trace 3 when it comes to an extra toggle. Sometimes there I can see something like a spike.  You wrote: Most likely setup or hold timing of inPIX_CLOCK has been violated here.  That's what I can't understand, because inPIX_CLOCK is a signal coming from another device. I have no possibility to change it. So I used a DFF to get it synchronous to my internal clock, which is coming from a 80MHz-Oscillator (on global clock pin 'clk').

[Altera_Forum]

It's normal behaviour with unrelated signals. A single DFF isn't enough synchronization to use the output as a ripple clock. It should work with a second DFF level. If the delay is an issue, you can operate both FF'S on different clock edges.

[Altera_Forum]

Ahh, should it look like this schematic? 

I will check whether the delay is an issue. But, it's not clear to me why I need two DFF. Is there an explanation for this 'workaround'?  When I do not use the Input for a rippleclock, is it enough to use only one DFF to synchronize it with my clock?

[Altera_Forum]

I have tested the 'double DFF' as in schematic2.jpg and it works! Thank you!

[Altera_Forum]

--- Quote Start ---  When I do not use the Input for a rippleclock, is it enough to use only one DFF to synchronize it with my clock?  --- Quote End ---   Altera recommends using always 2-stage sync, but I'm using it only in special cases.