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we wer doing Post synthesis simulation.
For that we use Altera Quartus Prime Standard Edition 15.1 in linux,we have qpf file with which we tried to generated .vho and .sdo file by the following link http://cseweb.ucsd.edu/classes/fa10/cse140l/lab2/lab2_tutorial_timinig_simulation.pdf (http://cseweb.ucsd.edu/classes/fa10/cse140l/lab2/lab2_tutorial_timinig_simulation.pdf) we were only able to generate .vho file,for the cyclone v device,please help me with any changes to be made to generate .sdo or .sdf file.Link Copied
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Hi,
The EDA netlist writer does not currently support gate-level simulation for the V-Series Hard IP for PCI Express® MegaCore® Function. https://www.altera.com/support/support-resources/knowledge-base/solutions/rd12102013_720.html Kindly refer previous threads also. https://alteraforum.com/forum/showthread.php?t=36762 https://alteraforum.com/forum/showthread.php?t=50750 Let me know if this has helped or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)- Mark as New
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Sir,
Thank you very much for the clarity. I have seen the Below things.Let me clear another question Is Timing Quest timing Analysis Possible. If Yes, could you share some procedures to follow the process of Timing Quest timing analysis in same Quartus Prime standard Edition 15.1 version and for the same Cyclone v family devices. --- Quote Start --- Hi, The EDA netlist writer does not currently support gate-level simulation for the V-Series Hard IP for PCI Express® MegaCore® Function.https://www.altera.com/support/support-resources/knowledge-base/solutions/rd12102013_720.html Kindly refer previous threads also.https://alteraforum.com/forum/showthread.php?t=36762 https://alteraforum.com/forum/showthread.php?t=50750 Let me know if this has helped or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation) --- Quote End --- Thanks and Regards Shyam K
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