I would like to use Parallel Flash Loader with Cyclone V GT (with PCIe).The Cyclone V GT FPGA Development Board using the MAX V CPLD 5M2210 as System Controller. Reading AN-487 it's seem I can connect the Flash device directly to the FPGA and save the CPLD as shown in ug_pfl.pdf, can it be done? https://www.altera.com/documentation/sss1411439280066.html https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an478.pdf Is there any other option to configure the FPGA (with the PCIe core) that the PCIe will be ready when the PC is booting? Is there any sample design I can use?
Hi,Refer to page 241. https://www.altera.com/en_us/pdfs/literature/hb/cyclone-v/cv_5v2.pdf I think you are looking for Configuration via Protocol (CvP) Kindly refer the below link. https://www.altera.com/documentation/nik1412546950394.html#nik1412546833714 Let me know if this has helped or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)