Hi,My end goal is to implement Source Synchronous interface with Cyclone 10 GX Transceivers. For transmit, can I use one transceiver as a clk line and drive 4 other transceiver as data line by controlling the phase of 4 data lines wit the clock line?
Please see the document at the following link: page 70 figure 16 https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-10/ug_cyclone1... in Which input reference clock which drives ATX PLL, FPLL, CMUPLL, then the output of PLLs drives Clock Generation Block (CGB) , after that the output of Clock Generation Block (CGB) drives the registers at the PMA section of transceivers.My question is : Is there any limitation by using the same reference clock to drive 5 transceiver then to use one of them as clock and 4 of them as data to implement source synchronous interface at 2.5 Gbps ( Clock will be 1.25 Ghz ) ?
Background and Questions:1- Background: For the source synchronous interface with Cyclone 10 GX transceiver, I am planning to use the following clock arrangement (Please see the attachment file): You can also find the same figure at page 70 Figure 16 in the following document: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-10/ug_cyclone1... https://alteraforum.com/forum/attachment.php?attachmentid=15624&stc=1 There are 3 locations in the figure shown below: 1- Input Ref Clock Pin 2- PLL Clocks Driving Transceiver Serializer 3- Transceiver Output Pins question: I want to adjust the clock phases of PLL clocks which are driving serializer based on the rising edge of input ref clock pin(Please note that there will be only one ref input clock pin for all 5 transceivers ) for all 5 transceiver which are going to be used in source synchronous interface ( 4 data and 1 clock ). is there any limitation or restrictions for implementing this configuration?
please note that the transceiver clock (1.25 ghz which gives 2.5 gbps ) will be integer multiple of input clock frequency for the alignment purposes.