sensitivity list. VHDL

Altera_Forum · ‎11-05-2009

Hello,

Maybe this is an elementary question, :D.

Why I need to add all the signals that I use in a process to the sensitivity list.

If I add them or not, I am getting the same results.

Thanks.

Altera_Forum · ‎11-05-2009

The sensitivity list is used only during simulations in VHDL

It shouldn't affect your final circuit :)

Regards,

Thiago

Altera_Forum · ‎11-05-2009

VHDL was written a long time ago and for simulation. I'm guessing simulators back then just looked at the sensitivity list, and weren't able to infer what should be in there. I think VHDL now lets you put a * or something like that to imply "whatever you need in here". I forget the exact syntax. (Technically, it might help readability too, since you have a location to determine what all the sources are, but I doubt it's overly useful for that.)

Altera_Forum · ‎11-05-2009

--- Quote Start ---

VHDL was written a long time ago and for simulation. I'm guessing simulators back then just looked at the sensitivity list, and weren't able to infer what should be in there. I think VHDL now lets you put a * or something like that to imply "whatever you need in here". I forget the exact syntax. (Technically, it might help readability too, since you have a location to determine what all the sources are, but I doubt it's overly useful for that.)

--- Quote End ---

This is all correct. Missing signals in a sensitivity list will give a warning in synthesis, and will give incorrect results in simulation.

Sensitivity lists are useful as they can help speed up simulation by ignoring events on anything thats not important. But the VHDL 2008 standard now lets you do this:

process(all)

to let you be sensitive to all signals declared in the entity. Not sure if quartus will compile this yet though, but it should work fine in newer versions of modelsim.

Altera_Forum · ‎11-06-2009

I am not completely with you about the role of the sensitivity list. For me, it is not only a tool for the simulator, it can also impact the synthesis.

For example, take the following codes. The first process has a sensitivity list with all the signals that are read during the process, and this lead to a combinatorial circuit.

The second process misses the b input in its sensitivity list. This implies that if a stays at the same level and b changes, the process is not activated and the output is not modified, so this leads to a latch in the circuit, so the process is no more pure combinatorial.


process(a, b)
begin
    if a = '1' and b = '0' then
        c <= '1'
    else
        c <= '0'
    end if;
end process;


process(a)
 begin
    if a = '1' and b = '0' then
        c <= '1'
    else
        c <= '0'
    end if;
end process;

Altera_Forum · ‎11-06-2009

This may be true, but the fact is when you actually synthesise it it doesnt produce a latch. It warns you that b should be in the list and then just generates the logic as the first example.

Altera_Forum · ‎11-06-2009

But that means that the synthesis tool does not follow the rule of VHDL. It is quite strange, no ?

Altera_Forum · ‎11-06-2009

Different synthesis tools may behave differently in this respect - i.e. one may produce a latch, another may not. It is exceptionally bad practice to ignore the sensitivity list on the assumption that the synthesis tool "will sort it out". The sensitivity list is there for a reason.

I think it was VHDL 2008 (aka VHDL 2006 as that was when it was drafted) that introduced the "all" in the sensitivity list - whilst Modelsim (uurrrggghh) may support this, be careful because your synthesis tool may not - Xilinx 11.1 definitely does not.