setup violation problem

[Altera_Forum]

Hello, 

I have a problem related to timing setup violation, my device is EP2C20F484C7, and I use classic timing analyzer as timing analysis tool. In addition, I use one global clock running at 50 MHZ. Since I choose All Paths for the hold time optimization in Fitter, there is no hold violation in the report. But setup violation occurs, and clock skew is large and negative. For example, one path information is as follows: fmax is 31.67mhz, setup relationship between ource and destination is 10ns, largest clock skew is -12.701ns, micro clock to output delay of source is 0ns, micro setup delay of destination is -0.038ns, longest register to register delay is 3.126ns. Therefore, the slack is negative and timing requirements are not met. I tried to set multicycle to relax timing setup check. Though Setting multicycle indeed reduces some setup violation, more new setup violative paths occur. How to figure it out?:confused:

[Altera_Forum]

If you can figure out what causes these clock skews it will be easier to solve the problem. Are there any generated clocks, any gated clocks or some register that act on different flanks?  

 //Ola

[Altera_Forum]

Thank you for reply, very helpful. I use lpm_counter to generate some signals as clocks. I don't know whether it is the reason that causes the clock skew. If it is, how can I rectify and optimize my design? It seems that sometimes I should need to use internal combinational logic to generate some clocks, and I know it may cause clock skew, how can I fix it?

[Altera_Forum]

I'm not an expert but I have some ideas (in no order of significance): 

 1. Use clock enables instead of counter clocks (preferably in a process to avoid gated clocks) 2. You could try using a pll to generate the lower clock 3. I think you can assign the counter signal as an global signal to help the router do it's job  Best Regards, Ola Bångdahl

[Altera_Forum]

Did you try to run the code onto your FPGA as well? Most probably the timing analyzer doesn't know (because you did not tell him) that he is crossing two different clock domains so the skew is only apparent. If this is true, you will see your FPGA working correctly. Try and let us know.

[Altera_Forum]

This is likely a design for which the caveats at http://www.alteraforum.com/forum/showthread.php?t=2388 should be carefully considered. That thread has a lot more detail on# 1 and# 2 in Ola Bångdahl's post and additional considerations.

[Altera_Forum]

--- Quote Start ---  Did you try to run the code onto your FPGA as well? Most probably the timing analyzer doesn't know (because you did not tell him) that he is crossing two different clock domains so the skew is only apparent. If this is true, you will see your FPGA working correctly. Try and let us know.  --- Quote End ---     Thanks for your reply. I run the code onto my FPGA and it was working correctly. The waveform I observed in the oscillograph was perfect without any problem, no glitch at all. However, when I tried to add a few more codes to my design such as the sort of "and" logic(very simple logic code). I found out my FPGA wasn't working correctly. There're a few glitches in the waveform. I guess it may be still the timing problem. What do you think?

[Altera_Forum]

--- Quote Start ---  I'm not an expert but I have some ideas (in no order of significance):   1. Use clock enables instead of counter clocks (preferably in a process to avoid gated clocks) 2. You could try using a pll to generate the lower clock 3. I think you can assign the counter signal as an global signal to help the router do it's job   Best Regards, Ola Bångdahl  --- Quote End ---     Thank you for your suggestions, I will look into my code and try to optimize my design.

[Altera_Forum]

I did several simulations and found out that several clock paths acted as ripple or gated clocks due to some clocks generated by counter, which caused gliches and effected the timing. Thank you all for many useful ideas, I will try to modify my code.

[Altera_Forum]

Have a look at the points where your glitches appear and place a clock enable just before every stage that generates glitches. ;)