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signal tap logic analyser problem!!! (STP)

Altera_Forum
Honored Contributor II
‎03-03-2013 08:47 AM
1,041 Views

Hi, 

 

anyone know is there any known issue in 12.1 and 12.1sp1 QII signal tap logic analyser? 

 

1) First, when i click run analysis / autorun analysis, the signal tap keep remaining in "waiting for trigger" stage even i didn't sent any trigger signal 

2) Without changing anything, i re-compile the design again. 

3) Now, i click run analysis / autorun analysis again, and the signal tap is working! 

 

I diff the the 2 fitter db file and found that there is a lot of different and i suspect maybe this different routing and placement make the stp working in 2nd compilation. 

 

This make me very embarrassing because many times i need to re-compile the design for 2 times in order to make the stp working! 

Anyone can help? 

 

Thanks, 

fpga89
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Altera_Forum
Honored Contributor II
‎03-04-2013 11:30 PM
279 Views

Seem like no other user experience my problem? :(

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