simple verilog to vhdl translation question

[Altera_Forum]

hello, 

 in a verilog module i found a declaration, that is,  output reg ack;  in vhdl translation, i can simply write :  signal ack;  am i right??

[Altera_Forum]

Almost right! 

 The fact that the verilog is  output reg ack;  states that the signal ack is an output from this module.  In your VHDL you need to ensure that the signal ack is defined as an output port on your entity.  entity test_e is  port  (  ...  ack : out std_logic  ...  );  end entity test_e;   also remember that in VHDL you will not be able to put an output signal on the Right hand side of an expression. i.e you may need an intermediate signal and assign that to your module output

[Altera_Forum]

another one verilog declaration: 

 reg [31:0] internal_regs[3:0]  how the codes in vhdl looks like?

[Altera_Forum]

reg [31:0] internal_regs[3:0] 

 This is a 2 dimensional array i.e. an array of 16 * 32 bit values  You will need to define a type like   type regs_type is array (0 to 15) of std_logic_vector(31 downto 0)  then a signal  signal internal_regs : regs_type;  elements are references as  internal_regs(0) <= X"12345678";  or for bit access  internal_regs(0, 1) <= '0';   etc  Hope this helps

[Altera_Forum]

thx. really help me. i added to your reputation. Another question: 

 Verilog codes:   reg [31:0] internal_regs[3:0]; input [31 downto 0] dati;  always@(posedge clk) begin .. internal regs[addr[4:2]] <=dati;  .. end  I have write my vhdl code for the line 70 as:  internal_reg(addr(4 downto 2)) <= dati; --line 70  but i got the following error: Error (10381): VHDL Type Mismatch error at wb_prom.vhd(70): indexed name returns a value whose type does not match "integer", the type of the target expression  how to change the code in line 70??

[Altera_Forum]

Is it because you wrote "internal_reg" instead of "internal_regs"?

[Altera_Forum]

nope..sorry..internal_regs what i wrote my vhdl programme..with 's'

[Altera_Forum]

It seems that you are trying to write three bytes 

 internal_reg(addr(4 downto 2))  into a 32-bit register, so you should adjust the indexes in order to write 4 bytes instead of 3.

[Altera_Forum]

i cannot do that because dati is 32 bits width. I have an idea which is, i must convert the addr(4 downto 0) to integer.in that means internal_regs(integer) which corresponds one of the array of 32 bits. but to convert this (4 downto 2) into integer is another problem. i have tried conv_integer(addr(4 downto 0)) but failed

[Altera_Forum]

Array indexes have to be an integer 

 so for  internal_reg(addr(4 downto 2)) <= dati; --line 70  you need to cast addr(4 downto 2) into an integer  something like  include the library  use ieee.std_logic_unsigned.all   internal_reg(to_integer( unsigned(addr(4 downto 2)))) <= dat;  you need to cast a std_logic_vector to an unsigned, then an unsigned to an integer.

[Altera_Forum]

I think it should be (3 downto 0) to be an integer

[Altera_Forum]

4 downto 0 must not be changed. i did what you tell but i got error: 

 to_integer is used but not declared.    i already added  use ieee.std_logic_unsigned.all

[Altera_Forum]

My mistake 

 You also need  use ieee.numeric_std.all;  http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf  Has some really good info on this kind of stuff