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simulating crc error using ederror_inject jtag instrucrion

Altera_Forum
Honored Contributor II
‎06-17-2016 10:04 AM
1,089 Views

Hi all, 

 

I am trying to verify the crc feature for SEU mitigation in Stratix IV device . While trying to inject error using ederror_inject jtag instruction , the data being written into fault injection register is shifted by one bit. What should be done to write the proper data into fault injection register? 

 

Thanks in advance
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