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simulation on the internal clock of cpld

Altera_Forum
Honored Contributor II
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is there a way to make a simulation on the internal clock of cpld in the model sim without connecting it to the card with the cpld? 

i mean if i can simulate with the vhdl file i got from the mega function on the quartus? . 

i am trying to simulate the vhdl code i wrote with the mega function vhdl code from the quartos and for the internal clock of the cpld i got "u" ,it doesnt recognize the clock. 

is there other way to simulate the internal clock?
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Altera_Forum
Honored Contributor II
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I guess you're talking about MAXII devices? The internal clock should be generated in the MAXII specific simulation library (hopefully). Did you check the ModelSim log for warnings about missing instances?

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