single FPGA as TXR and RXR

[Altera_Forum]

Hello, 

  I have just been exposed to working with FPGA. I want a single FPGA to act as the transmitter(say, generates bits) and as a Receiver(say, to test for bit error) . How do I make the fpga to run both the programs simultaneously? And what are the factors that I should keep in mind while trying to get the output right?  Thanks in advance !

[Altera_Forum]

--- Quote Start ---  Hello,   I have just been exposed to working with FPGA. I want a single FPGA to act as the transmitter(say, generates bits) and as a Receiver(say, to test for bit error) . How do I make the fpga to run both the programs simultaneously? And what are the factors that I should keep in mind while trying to get the output right?  Thanks in advance !  --- Quote End ---    you haven't been told what comms system you are targeting FSK, QPSK other QAMs...etc? That is most crucial information for you

[Altera_Forum]

firstly, I am using a PRBS generator to send bits . The BER tester and the PRBS generator , both work are to be done by one FPGA. How do I make sure that both the programs rum simultaneously?>

[Altera_Forum]

That is very simple then. You already done something like that but you were not sure about rx ready signal. 

Your prbs1 sends data, add some dummy delay e.g. few registers in the way and send in parallel a valid out signal delay as data your prbs2(copy of prbs1) waits for valid out and runs. compare delayed data(received) with prbs2 output.

[Altera_Forum]

FPGA design is by nature parallel. Every circuit that you define to run in the FPGA will always be running all the time. So, if you instantiate a PRBS generator and a PRBS receiver, they will naturally both be running. 

 Your question makes me think you are coming from a software background. You will need to keep in mind that an HDL like Verilog or VHDL is fundamentally different from a programming language like C, in that C is sequential and an HDL describes hardware.  I hope this helps.

[Altera_Forum]

It is common practice to have Tx and Rx circuitry in one FPGA. 

It is also useful to run two PRBSs one at Tx and at Rx for testing. Nothing software about it. Each one starts separately

[Altera_Forum]

Thank you everyone ! At the receiver, the serial data should be stored in a buffer variable ? It woiuld be nice if someone can explain as to how the bits generated from the txr will be received at the receiver bit by bit as and when the txr send them .