Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

speed grade

Altera_Forum
Honored Contributor II
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Hi, 

 

if i'm using CYCLONE III EP3C40F484C6 - that means that its speed grade is 6 . right? 

 

Thanks, 

Fina.
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Altera_Forum
Honored Contributor II
711 Views

Hi Fina, 

 

Yes, of course, 

 

You can see the Device Packaging Ordering Information in Cyclone III Handbook page 1-12.. 

 

Here the link : http://www.altera.com/literature/hb/cyc3/cyclone3_handbook.pdf
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Hi, 

 

if i'm using CYCLONE III EP3C40F484C6 - that means that its speed grade is 6 . right? 

 

Thanks, 

Fina. 

--- Quote End ---  

 

 

 

Hi, 

 

yes that's right. Keep in mind that it is not an exact indication of the max speed of the FPGA.  

 

Kind regards 

 

GPK
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Altera_Forum
Honored Contributor II
711 Views

Thanks a lot for your answers :) :) :)  

 

how can i know device max speed?
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Altera_Forum
Honored Contributor II
711 Views

 

--- Quote Start ---  

Thanks a lot for your answers :) :) :)  

 

how can i know device max speed? 

--- Quote End ---  

 

 

Hi, 

 

sorry, I was not exact enough in my post. The timing for e.g. PLL's, I/O, I/O standards could be used to decide which speed grade do you need for your application. What I mean in my first post is was that the internal clock speed depends on your design. When you look into the datasheet you find e.g. a number for the clocktree speed ( C8 402 MHz). This doesn't mean that your design could run at this speed.  

 

Sorry for any confusion. 

 

Kind regards 

 

GPK
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Altera_Forum
Honored Contributor II
711 Views

Thank you !

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