synthesis of several "if..if...if "sentence.

[Altera_Forum]

always @(posedge clk or negedge rst)begin 

if(!rst)begin  .....  end  else begin  if(a)  ....  if(b)  ....  if(c)  ....  end end  I found that the synthesised circuit is priority,i.e.there are selectors.But I want them to be parallel!How can I do with that? Please!

[Altera_Forum]

Verilog states cases statements are priority encoded. If it's obvious it doesn't need priority, synthesis can often figure it out. Historically most people got around this with parallel_case and full_case attributes. System verilog now has "unique" and "priority" attributes. I'm sure there are some nice quick descriptions on the web/wikipedia that describe those two. If you want the long explanation, go to: 

http://www.sutherland-hdl.com/papers/2005-snug-paper_systemverilog_unique_and_priority.pdf

[Altera_Forum]

thank u! 

But I don't mean the "case" sentence.so parallel_case and full_case attributes don't help. I got the situation that 8 "if" sentences need to be included in the always block,so the priority circuit decreases the fmax. I have to make them parallel so that increase the Fmax.

[Altera_Forum]

You should clarify in which regard you mean priority is involved with the present construct. I don't see any priority related behavior at all. It may be of course, if the conditional expressions are setting the same variables.

[Altera_Forum]

Yes,I set the same variable in the three conditional expressions.Is that the problem?

[Altera_Forum]

Yes by making multiple assignments in an if cascade you ended up coding priority into the assignment. You could do a one-hot mux like this assuming a, b, and c are asserted mutually exclusively: 

 always @ (a or b or c) begin case ({c, b, a}) 3'b001: <expression>; 3'b010: <expression>; 3'b100: <expression>; default: <expression>; // this case can never happen if only one of a, b, or c are ever enabled at any given time endcase end

[Altera_Forum]

--- Quote Start ---  Yes,I set the same variable in the three conditional expressions.  --- Quote End ---   Setting the same variable can't be parallel, except if the conditions are mutual exclusive, which refers to an if () .... else if()....else if() ....  construct.  It's not a problem of HDL syntax, just of feasible logic respectively thinking.

[Altera_Forum]

Thank U so much! It's helpfull!!

[Altera_Forum]

Thank U so much! It's helpfull!! 

   --- Quote Start ---  Yes by making multiple assignments in an if cascade you ended up coding priority into the assignment. You could do a one-hot mux like this assuming a, b, and c are asserted mutually exclusively:  always @ (a or b or c) begin case ({c, b, a}) 3'b001: <expression>; 3'b010: <expression>; 3'b100: <expression>; default: <expression>; // this case can never happen if only one of a, b, or c are ever enabled at any given time endcase end   --- Quote End ---  

[Altera_Forum]

Make sure though that only A, B, or C can be asserted at any given time, otherwise that "one-hot" encoding will fail and the default case will be used. In other words, using the example above if C,B,A (concatenated together) came out to anything but 001, 010, or 100, then the default expression would be decoded.

[Altera_Forum]

In SystemVerilog you can use the unique attribute to if else if else statement. 

 always @(posedge clk or negedge rst)begin if(!rst)begin ..... end else begin unique if(a) .... else if(b) .... else if(c) .... end endDuring simulation you will get error if any of a, b or c are true simultaneously.