Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

testing procedure

Altera_Forum
Honored Contributor II
‎07-07-2009 10:49 AM
842 Views

hi 

iam hosam  

iam a new member in this field of FPGA testing using JTAG and 

BSDL 

i just want a guide to get the procedure of testing FPGA using JTAG 

(just main points) to complete my degree of master  

i've read 4 monthes about BSDL and JTAG and now i try to begin doing that 

can anyone help me?
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.