Reset circuit / Cyclone III

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Reset circuit / Cyclone III

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Hello,

I am new designer with Altera Devices and not familiar with it so I would appreciate advices from experienced users, concerning Reset circuit.

I am used to put reset circuit for µP and Xilinx devices, that holds low the Configuration Reset pin (nCONFIG here), while all the power supplies are not settled.

I had a look to a couple of Altera boards schematics and this pin is always tied to VCCIO via a 10k pull-up.

Is it still a good practice to use a Voltage supervisor reset circuit that will hold low nCONFIG and release it 200 ms after ?

Any bad experience in doing (or not) this?

Another question: what is the exact POR voltage threshold for VCCINT/VCCIO or where can I found it?

Thank you for your answers.

> Any reply ?

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