Reset circuit / Cyclone III

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Reset circuit / Cyclone III

1,023 Views

Hello,

I am new designer with Altera Devices and not familiar with it so I would appreciate advices from experienced users, concerning Reset circuit.

I am used to put reset circuit for µP and Xilinx devices, that holds low the Configuration Reset pin (nCONFIG here), while all the power supplies are not settled.

I had a look to a couple of Altera boards schematics and this pin is always tied to VCCIO via a 10k pull-up.

Is it still a good practice to use a Voltage supervisor reset circuit that will hold low nCONFIG and release it 200 ms after ?

Any bad experience in doing (or not) this?

Another question: what is the exact POR voltage threshold for VCCINT/VCCIO or where can I found it?

Thank you for your answers.

> Any reply ?

Link Copied

0 Replies

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.