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timing constrain of adc and fpga interface with data,fco,dco signals.

Altera_Forum
Honored Contributor II
‎07-08-2013 08:12 AM
2,310 Views

hi. 

In my design, there is a ADC chip adc9228. The ad9228 output serial data D+/D- with data clock DCO+/DCO- and frame clock FCO+/FCO-. DCO latches data at both edges.FCO's rising edge indicates the first bit of adc data. How to constrain timings with timequest?  

 

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Altera_Forum
Honored Contributor II
‎07-19-2013 08:43 AM
1,560 Views

Can anybody help me?

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Altera_Forum
Honored Contributor II
‎07-20-2013 10:06 AM
1,560 Views

I would just create a clock with the entire period, quartus will now to do timing analysis on the falling edge by analyzing your rtl code.

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