to extract state diagrams from vhdl/verilog code

[Altera_Forum]

I am implementing a RS232 controller on FPGA. I have the Verilog code for transmitter and reciever. can anyone give the details how to extract the state diagrams or state machines from this code. I am using Quartus II sofware. I attached code too.

[Altera_Forum]

have you tried going to Tools => Netlist Viewers => State Machine Viewer after doing Analysis and Elaboration?

[Altera_Forum]

Hi, I tired but it shows the message "Design has no state machine". could u help me out

[Altera_Forum]

It is quite easy to extract manually the state machine design in this code. Just have a look at the case(state) statements. 

I'm not sure, but the state machine may not be recognized by Quartus because there is no reset state. I could be wrong though. That said you should really add a reset state to this code. Nothing here tells how the fsm should start.

[Altera_Forum]

could u please add the reset state in that code and send it to me. If we cant generate in quartus, is there anyother software to generate the state machine.

[Altera_Forum]

I don't know Verilog well enough to be sure to post correct code, but I'm sure any good Verilog book has lots of examples for FSM's. 

The problem isn't that Quartus doesn't synthesize your code. It should still compile and run on an FPGA. It is just that your code doesn't seem to be recognized as a state machine, and as such isn't optimized and can't be shown in the state machine viewer.

[Altera_Forum]

I shall I translate it to other language like VHDL,C. so that u can correct the code.

[Altera_Forum]

--- Quote Start ---  I shall I translate it to other language like VHDL,C. so that u can correct the code.  --- Quote End ---    Hi,  I found the root cause why the statemachine extraction fails. It is not allowed to access the state value with an index.  // if(Baud8Tick && next_bit && state[3]) RxD_data <= {~RxD_bit_inv, RxD_data[7:1]};  For testing I changed the line to :   if(Baud8Tick && next_bit && state==4'b1001) RxD_data <= {~RxD_bit_inv, RxD_data[7:1]};  I have a small project attached.  Kind regards  GPK

[Altera_Forum]

Hello all!  

I don't want create new topic with my problem (like this). I did simple Write-Read RSR232 design by using two files from this topic (&#1072;sync_receiv&#1077;r.v and &#1072;sync_tr&#1072;nsmitter.v).   But some (0-3) first symbols from COM-port are wrong:( Where is my error? Who helps me?  Thanks all!  P.S.: Quartus 9_1 design is "RS_Test.zip" P.P.S.: VS'2008 design is "com.zip"