We use Quartus19.1 to generate a .jbc file for the EPCS128 connected to a EP4CE6F17I7N FPGA via the Active Serial interface..
On our board we use the Jam STAPL Byte-Code Player Version 2.2 software to program the Serial Configuration Device via JTAG.
The programming is working, but propably during the time of access to the Serial Configuration Device via the Serial Flash Loader (SFL) some IOs of the FPGA do not have anymore this Weak Pull-ups as we expect.
(E.g. when I start programming the output (Pin B4) gets first input with weak Pull-up for a while and then just input or input with Weak Pull-down before it gets again ouput at the end.)
Is there any explanation of this behavior?
As I remember, we had similar effects in a old project, but only when we generated the .jbc file with Quartus newer then 13.1. Maybe that helps to find the problem.
Yes all pin are pulled to HIGH Z during configuration mode. When the device is booted successfully, unused pin will remain the same as what is set in Quartus. Meanwhile, used pin will go back to the state which is set in the design.
What you describe is correct. But I was talking about the pin state during programming of the Configuration Memory via JTAG-SFL-ASMI.
It seems that when the SFL is active, some IOs are not anymore with weak pull-ups.
Or do you say, that we can define the IOs of this SFL bridge, which gets loaded first, somehow in Quartus. How do we have to do it?
P.S. sorry for my poor english
The IO state is the same in all programming scenario.
You may change the unused pin state in user mode by following the guide below:
In our design the unused IOs are already set as input tri-stated with weak pull-up. And actually the Pin B4 is used as an output.
What about the IOs after the SFL from the generated .jbc file is loaded via JTAG and active? Can we also define them in this state of the programming?
As I wrote during programming of the Config. Flash via JTAG-SFL(Serial Flash Loader)-ASMI(Actice Serial Memory Interface), this output has not anymore a weak pull-up.
I'm sorry that I confused you. Actually it was always Pin R7 I talked about. We use this user output as Backlight-Enable signal in our design.
The picture I attached, shows that this output R7 (trace C3) is going low (instead high with weak pull-up) in the programming phase when the configuration memory gets accessed via JTAG-SFL-ASMI. Visible because the Chipselect ouput 'CSO' of the FPGA (trace C2) is toggling.
Before this phase of programming you can see that the output is high with weak pull-up. Which is as expected and I assume that this is the phase where the SFL bridge gets loaded to the FPGA via JTAG.
At the beginn and at the end of the picture the output is high, when the FPGA is in user mode.
Trace C1 is the CONF_DONE output of the FPGA.
So, my question. Way gets the user output R7 low during programming?