using ALTUFM_PARALLEL on MAX V

[Altera_Forum]

Well, my first thread has crashed... 

   --- Quote Start ---  Hi,   Since I have no response, I'll be simpler:   1) Is it possible to use the altufm_parallel (http://quartushelp.altera.com/14.1/mergedprojects/hdl/mega/mega_file_altufm_parallel.htm) function on MAX V devices? 2) Is there any protocol I missed in the user guide (http://www.alteraforum.com/forum/www.altera.com/en_us/pdfs/literature/hb/max-v/mv51007.pdf)? 3) How do you initialize/programme the UFM on Quartus II?     --- Quote Start ---  I'm attempting to use the altufm_parallel (http://quartushelp.altera.com/14.1/mergedprojects/hdl/mega/mega_file_altufm_parallel.htm) Megafunction, in read only mode. In that purpose, I used Qsys to configure my altufm_parallel block with 9 bits addr width, 16 bits word width and that it initialize itself with an .hex file. I generate the HDL file, add it to the project's librairie and then I put the altufm_parallel block to my block design file. My project compile and programme well on the Dev Kit, but when I try to measure my outputs on the GPIO Header it's permanently high. Even Though nbusy and data_valid signals seems to react on falling edge of nread, as expected of the waveform I find in the MAX V handbook. http://www.alteraforum.com/forum/attachment.php?attachmentid=10869&stc=1   --- Quote End ---    --- Quote End ---     Best regards.

[Altera_Forum]

Hi, 

 the parallel interface is explained in the document "Altera User Flash Memory (ALTUFM) IP Core User Guide", you can get it from here: https://www.altera.com/en_us/pdfs/literature/ug/ug_alt_ufm.pdf (https://www.altera.com/en_us/pdfs/literature/ug/ug_alt_ufm.pdf). Unfortunately there are no waveform examples for the parallel interface, but it seems to be pretty straightforward - wait until "busy" is 0, then apply "addr" and strobe "nread", wait until "data_valid" is 1, then get your data from "do". If in doubt you can also write a small testbench and simulate it in ModelSim.   Best regards, GooGooCluster

[Altera_Forum]

Hi, 

 I am NOT able to create ALTUFM_PARALLEL, with 8 bit data. I am using Quartus-II 12.1sp1 full edition.   As per Max V handbook, in the Parallel mode, it is possible to have Data Width anywhere from 3 to 16 bits. However my MegaWizard is only showing 16 bit data width and not any other option. Pl see the pic file.  Am I doing something wrong? Thanks in advance :-)  https://www.alteraforum.com/forum/attachment.php?attachmentid=11177

[Altera_Forum]

Hi, 

 the UFM is always 16 bit, but it looks like there's a way the MegaFunction only exposes 3 of those (which I fail to understand, but whatever).  Altera User Flash Memory (ALTUFM) IP Core User Guide (2014.08.18), page 25: "even though you can select an optional data register width of 3 to 16 bits using the altufm ip core, the ufm block always expects full 16 bits width for the data register. reading from the data register will always proceed from msb to lsb. the altufm ip core will always pad the remaining lsb of the data register with 1s if the user selects a data width of less than 16-bits".  BTW., when you instantiate UFM with Quartus 15.0.2, you can actually select any width from 3 to 16 bit. However, selecting 3 bit does not, as one might expect, allow you to use more address bits. This agrees with the user guide that says the excess bits are basically dropped.  So if you want to have 8-bit data with 10-bit addresses, I'd suggest you instantiate the UFM with 9 address bits and 16 data bits, use the 9 MSBs of your address vector for the UFM, and the LSB to mux between the upper and lower byte of the 16-bit data word.   Best regards, GooGooCluster

[Altera_Forum]

Hi,  

 Thanks for the reply.  I like your suggestion with 10 bit address and sticking with the default 16 bit data-width.  However, I preferred to use byte-wide data (and was willing to sacrifice some memory space, as UFM is hardwired for 16 bit data.)  Regarding "when you instantiate ufm with quartus 15.0.2", do you mean creating it using the MegaFunction Wizard, or actually when Instantiating the generated HDL component within my top level HDL code? I looked at the VHDL model provided by my 12.1sp1 version and datawidth is not a generic parameter, to be set by the user. Is this the case in the 15.0.2 version or you meant, using the MegaFunction Wizard?  Thanks again!

[Altera_Forum]

Hi, 

 I mean using the IP Catalog (which replaces the MegaWizard in Quartus 15) to create a new MegaFuction. There it gives you the option to set the port width. However, still only 9 address bits. You can probably also edit an existing MF from an older version, I did not try that.  Btw, I realised that my suggestion with 10 address bits and a byte mux would not work... the UFM has no write mask. If you need ten address bits, you've got to write a FSM that does a read modify write (except if you do read only).   Best regards,  GooGooCluster

[Altera_Forum]

Actually the write could be done using only the 9 bit of addr, (provided two write bytes are grouped together). This and few other reasons made me think of using 1 single byte of data, sacrificing some memory space.  

 I shall try this with the newer version and hopefully would be good to go! Thanks again!