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hi, currently i'm doing a project using a sensor which has pwm output. i'm already done the coding to read the pwm output. i would like to connect the pwm output from the sensor ti de2 board as input. can i just connect the pwm output to the GPIO pin on expansion header?
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Check the voltage compatibility first.
You will also need to connect a ground pin between your sensor and the DE2. If you are "looking" at the PWM signal using logic clocked in the FPGA, then make sure to add a synchronizer, i.e., PWM input -> synchronizer -> FPGA logic Cheers, Dave- Mark as New
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the sensor operating voltage is between 2.5 to 5.5V, so i want to use VCC5V from the GPIO to power up the sensor and assign one of the GPIO pin as the input and connect to the pwm output of the sensor. i'm using fpga internal clock 50Mhz . the pwm output is 147us per inch, using the 50MHz clock on the FPGA, 147us / 20ns = 7350 counts per inch.
do i need to use synchronizer? how to add one? thanks,- Mark as New
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--- Quote Start --- the sensor operating voltage is between 2.5 to 5.5V, so i want to use VCC5V from the GPIO to power up the sensor and assign one of the GPIO pin as the input and connect to the pwm output of the sensor. --- Quote End --- As I commented above, *you* need to look at the schematic for the board and make sure you use a voltage compatible with the I/Os on the board. I'm not going to tell you the answer, I want you to understand what it is you have to do whenever you want to interface to an FPGA. If you are using 5V to power the sensor, then it will output 5V logic levels. Its your job now to check that this will not damage the I/Os on the board. The things to look for are; a voltage level translator, a 5V FPGA, or voltage clamps. --- Quote Start --- i'm using fpga internal clock 50Mhz . the pwm output is 147us per inch, using the 50MHz clock on the FPGA, 147us / 20ns = 7350 counts per inch. do i need to use synchronizer? how to add one? --- Quote End --- A synchronizer is a common circuit used when crossing clock domains. Its used to reduce the chances of metastability. Google it. For your purposes, its two D flip-flops in cascade. The synchronizer ensures that the synchronized copy of the PWM signal asserts and deasserts synchronous to the 50MHz clock. That way if you are using the PWM signal to enable a counter, the enable signal is synchronous. Cheers, Dave

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