using lvds

[Altera_Forum]

G´day !! 

 I´m using an ADC with differential output (LVDS). It´s a device including 8 ADCs with Serial LVDS output. Data from each ADC is serialized and provided on a seperate channel. This serial data (data rate for each serial stream is 700Mbps maximum) is read with Cyclon III. What´s the best way to do this ? I found the ALTLVDS Megafunction, but i think this block has no sense, cause of the serialization factor of 1 for each channel used in my system. But what´s the best way to read and process the sampled input data ?? Is it possible to wire this LVDS Serial data direct to a PIO ???   hope someone can help me greets !!!

[Altera_Forum]

TO_BE_DONE

[Altera_Forum]

Hi josyb, 

 Is it means that 350MHz would get 700Mbps data rate? Cause of DDR.

[Altera_Forum]

--- Quote Start ---  Hi josyb,  Is it means that 350MHz would get 700Mbps data rate? Cause of DDR.  --- Quote End ---    Yes, it will.

[Altera_Forum]

--- Quote Start ---  Yes, it will.  --- Quote End ---    Hi josyb,  Thanks for you reply!  I'm going to using Stratix IVGX deivce, and have to use column I/O LVDS pairs to receive ADC output. I don't know the maximum speed of these column I/O LVDS pairs, and the datasheet only give the row I/O LVDS pairs speed range. Do you think the column I/O lvds pairs can run at 700Mbps or more than this speed?

[Altera_Forum]

--- Quote Start ---  I'm going to using Stratix IVGX deivce, and have to use column I/O LVDS pairs to receive ADC output. I don't know the maximum speed of these column I/O LVDS pairs, and the datasheet only give the row I/O LVDS pairs speed range. Do you think the column I/O lvds pairs can run at 700Mbps or more than this speed?  --- Quote End ---   The Device Datasheet doesn't mention any difference between Row and Column IO, so I'm pretty sure that 700 Mbps will be fine. But you can easily try that out ...

[Altera_Forum]

--- Quote Start ---  The Device Datasheet doesn't mention any difference between Row and Column IO, so I'm pretty sure that 700 Mbps will be fine. But you can easily try that out ...  --- Quote End ---    Hi josyb,  ADC's output speed is up to 1.6Gbps, even run at 2-lane mode, the LVDS pairs speed at FPGA side will be 800Mbps. If LVDS pairs connect to column I/O LVDS pairs, means shift register will run at 800MHz. Does core logic run at so high speed?

[Altera_Forum]

Jerry, 

 800Mbps will result in a 400 MHz clock,which is delivered by the ADC, usually 90 degree shifted (center-aligned). But this clock will only be used to shift the first 4 (5, 6, 7 or 8 ) stages resulting into two 4 (5,6,7 or 8) vectors that will then be combined to the final 8 (10,12,14 or 16) bit word. The ADC usually has a frameclock signal that you can derive a signal from to transfer the received word back into the base clock of 100 MHz which can be handled 'hands down' by the FPGA fabric The LTM9010 in 14-bit 2-Lane mode is only slightly more complicated in that it sends out a half-rate FR-clock, delivering two 14-bit samples every other base clock, but you can multiplex that back up to one 14-bit sample per clock.  Regards, Josy

[Altera_Forum]

Hi josyb, 

 Thanks for you reply.    --- Quote Start ---  delivering two 14-bit samples every other base clock,  --- Quote End ---   Is here should be 7-bit?  Do you have some thought about the synchronization among channels and devices?  Can i use internal system clock as the shift-regiters clock? And the ADCs' DCO signals can't be routed to FPGA?

[Altera_Forum]

--- Quote Start ---   Is here should be 7-bit?  Do you have some thought about the synchronization among channels and devices?  Can i use internal system clock as the shift-regiters clock? And the ADCs' DCO signals can't be routed to FPGA?  --- Quote End ---   The picture on page 8 in the data-sheet of the LTM9010 shows 2 ADC words are transmitted per FR-cycle (using 7 DCO clocks) You can use an internal clock for the DDR-IN and the following shift-registers, but then you will have to align the incoming LVDS data using extra logic. It would save you from routing the 6 * 2 (*2) wires for the DCO and the FR signals. If you have enough clock inputs available on your Stratix device, I would recommend using DCO and FR; it gives you a nice static timing closure.  Synchronisation between devices: the only concern is that the encoding clock is synchronous for all ADC-chips: keeping them equal in length is one thing. The other is perhaps drive them from a clock distribution IC giving you very tight timing, it depends on your requirements.  Regards,  Josy

[Altera_Forum]

--- Quote Start ---  The picture on page 8 in the data-sheet of the LTM9010 shows 2 ADC words are transmitted per FR-cycle (using 7 DCO clocks) You can use an internal clock for the DDR-IN and the following shift-registers, but then you will have to align the incoming LVDS data using extra logic. It would save you from routing the 6 * 2 (*2) wires for the DCO and the FR signals. If you have enough clock inputs available on your Stratix device, I would recommend using DCO and FR; it gives you a nice static timing closure.  Synchronisation between devices: the only concern is that the encoding clock is synchronous for all ADC-chips: keeping them equal in length is one thing. The other is perhaps drive them from a clock distribution IC giving you very tight timing, it depends on your requirements.  Regards,  Josy  --- Quote End ---    Hello Josy,  Thanks for you help.  I'm testing LVDS module in Quartus II, can you tell me about implementing bitslip method?

[Altera_Forum]

--- Quote Start ---   I'm testing LVDS module in Quartus II, can you tell me about implementing bitslip method?  --- Quote End ---   You don't need a bitslip module, as you can derive a signal from the FR-signal to clock the final two 14 bit words into to the original base-clock domain.  Regards, Josy

[Altera_Forum]

--- Quote Start ---  You don't need a bitslip module, as you can derive a signal from the FR-signal to clock the final two 14 bit words into to the original base-clock domain.  Regards, Josy  --- Quote End ---    Hi Josy,  I know, currently i'm testing one ADC chip implemented by using altlvds module. If the parallel lvds output data doesn't align with word boundary, the core logic should generate one pulse to feed rx_data_align port. Untill the output data align with word boundary. Here, is the word boundary also can be indicated by FR-signal?

[Altera_Forum]

Jerry, 

 I haven't used altlvds, way too complicated for me :) I assumed you were writing your own deserialiser.  Regards,  Josy

[Altera_Forum]

--- Quote Start ---  Jerry,  I haven't used altlvds, way too complicated for me :) I assumed you were writing your own deserialiser.  Regards,  Josy  --- Quote End ---    Hi Josy,  I remember that you used AD9222 deivces. How about the ADC's dirving circuit design? I'm thinking about these circuit. Our previous design used AD9218, and AD8138 as ADC's driver. However, for multi-channels LVDS output ADCs, ADI doesn't recommend using amplifiers as driver. The reason is that:"the noise of performance of most amplifiers is not adequate to achieve the true performance of the AD9222/AD9633/AD9681." Our application is of dc-coupled, so amplifiers are very suited for our app.  Do you think the transformer coupled configuration is belone of DC-coupled desgin?

[Altera_Forum]

--- Quote Start ---  The serialisation factor in your system is actually 14. The ALTLVDS does not support this, but you could set it to handle a deserialisation of 7 bits and concatenate two 7-bit packets into one 14 bit. ALTLVDS however uses a PLL to sample the inputs, so if you have multiple devices, ADCs in this case) you may run out of PLLs. However as the outputs of the ADC are nicely source synchronous and are accompanied by a dataclock and a frame-indicator , you can easily deserialise the ADC data channels with simple shiftregisters. Feed the inputs into a DDR-In block and then serialise the 2 bits in a 7-bit shiftregister each. assemble the 2 7-bit buses into a 14-bit bus and define the right moment to register it.  You need to do some work to constrain all this though. I have done this for ADS527x and AD9222 octal ADCs, unfortunately my code is in AHDL (I do use VHDL nowadays).  --- Quote End ---    Hi Josy,  If i run out of PLLs, how to connect the rest DCO signals? Can i connect them to normal LVDS pairs?

[Altera_Forum]

Jerry, 

 you connect the DCO signals to LVDS clock input pins on the FPGA.

[Altera_Forum]

--- Quote Start ---  Jerry,  you connect the DCO signals to LVDS clock input pins on the FPGA.  --- Quote End ---    1. Must DCO be connected to clock input? 2. Does your FPGA has 8 pair LVDS clock input pins? What's your fpga PN? For you said, you have processed several octal channels ADCs, in single FPGA? 3. My fpga only has 4 pairs dedicated LVDS clocks, which on left and right sides of the FPGA. Can i connect dco to dedicated clock input pins on top or bottom sides of the FPGA? And configure them as LVDS input. http://www.alteraforum.com/forum/attachment.php?attachmentid=13048&stc=1  The PLL_[L1,L4,R1,R4]_CLK* are the LVDS module dedicated clock, which will feed to the dedicated PLL. Also, this FPGA has many other normal clock input pins, as below figure shows. My question is that can i connect the ADC DCO signals to these clock input pins regardless of where they are (top or bottom or left or right sides)? http://www.alteraforum.com/forum/attachment.php?attachmentid=13049&stc=1

[Altera_Forum]

--- Quote Start ---  1. Must DCO be connected to clock input? 2. Does your FPGA has 8 pair LVDS clock input pins? What's your fpga PN? For you said, you have processed several octal channels ADCs, in single FPGA? 3. My fpga only has 4 pairs dedicated LVDS clocks, which on left and right sides of the FPGA. Can i connect dco to dedicated clock input pins on top or bottom sides of the FPGA? And configure them as LVDS input. The PLL_[L1,L4,R1,R4]_CLK* are the LVDS module dedicated clock, which will feed to the dedicated PLL. Also, this FPGA has many other normal clock input pins, as below figure shows. My question is that can i connect the ADC DCO signals to these clock input pins regardless of where they are (top or bottom or left or right sides)?   --- Quote End ---    Jerry,  1. The DCO LVDS signal is the high-speed output clock from the ADC. In Cyclone devices the easiest way is to use them as the IO-clock. I extrapolate this would also come easy in Stratix devices. The other way may be to use an internally PLL-generated clock and dynamically set the delay in the input cells to align the data with this clock. I haven't tried this as in Cyclone this definitely is not possible, but I think this could work in Stratix devices.  2. At the time I fed 4 octal 12-bit ADCs into an EP2C8F256. I had 4 of these feeding further into an EP2SGX60 (making 16 ADCs or 128 analog channels in total). This is the only time I used Stratix FPGA's.  https://www.alteraforum.com/forum/attachment.php?attachmentid=13050  I used the DCO of each ADC to clock in the data, and connected each DCO to a (regional) clock input.  3. How many ADC devices do you want to connect to which Stratix IV GX device?  Regards,  Josy

[Altera_Forum]

--- Quote Start ---  Jerry,  1. The DCO LVDS signal is the high-speed output clock from the ADC. In Cyclone devices the easiest way is to use them as the IO-clock. I extrapolate this would also come easy in Stratix devices. The other way may be to use an internally PLL-generated clock and dynamically set the delay in the input cells to align the data with this clock. I haven't tried this as in Cyclone this definitely is not possible, but I think this could work in Stratix devices.  2. At the time I fed 4 octal 12-bit ADCs into an EP2C8F256. I had 4 of these feeding further into an EP2SGX60 (making 16 ADCs or 128 analog channels in total). This is the only time I used Stratix FPGA's.  http://www.alteraforum.com/forum/attachment.php?attachmentid=13050&stc=1  I used the DCO of each ADC to clock in the data, and connected each DCO to a (regional) clock input.  3. How many ADC devices do you want to connect to which Stratix IV GX device?  Regards,  Josy  --- Quote End ---    Hello Josy,   Thanks for you reply.  1. Can DCO connect to IO-clock, which doesn't locate in the same IO-bank of the normal ADC output data lvds siganls connected? 2. There are 16 ADC clocks (DCO) that need to be connected to your EP2S60, and all of these DCO are connected to EP2S60's clock-IO, am i right? 3. I have 12 ADC devices. And my FPGA have total 16 normal clock-IO, exclude transceiver ref-clock. I don't think i can connect DCO to those transceiver ref-clock pins. My ADC PN is AD9633 and i want it run at 100M@10-bits, so the DCO output clock speed will be 500MHz.  BTW, When you place and route your ADC channels, did you make trace length equal constrain among all DCO signals and among all ADC output lvds signals? Is this trace length equal control necessary?

[Altera_Forum]

--- Quote Start ---  Hello Josy,   Thanks for you reply.  1. Can DCO connect to IO-clock, which doesn't locate in the same IO-bank of the normal ADC output data lvds siganls connected? 2. There are 16 ADC clocks (DCO) that need to be connected to your EP2S60, and all of these DCO are connected to EP2S60's clock-IO, am i right? 3. I have 12 ADC devices. And my FPGA have total 16 normal clock-IO, exclude transceiver ref-clock. I don't think i can connect DCO to those transceiver ref-clock pins. My ADC PN is AD9633 and i want it run at 100M@10-bits, so the DCO output clock speed will be 500MHz.  BTW, When you place and route your ADC channels, did you make trace length equal constrain among all DCO signals and among all ADC output lvds signals? Is this trace length equal control necessary?  --- Quote End ---    1) I'm not a Stratix expert, so I would need to study this further, but this is outside my scope. Perhaps somebody else will answer this question? 2) The DCO clocks (and data) go to the EP2C8 devices, as the EP2SGX60 didn't have enough LVDS Receivers. From the EP2C8's I have 4 wide-parallel LVCMOS buses feeding into the EP2SGX60. 3) You still didn't tell which Stratix IV device you are targeting? Although I have to repeat I'm not a Stratix expert at all. With 12 ADC devices you will need 12 * 6 or 96 LVDS inputs in total, and 12 of them need to feed into a clock input. Achieving timing closure at 1000 Mbps, using static .sdc constraints, may turn out to be difficult. And using the DPA feature in the ALTLVDS may then be a better approach.   I balanced all timing delays. On the picture the analog data is fed in from the right going left, I also fed the ADC clocks first going from the EP2SGX60 FPG to the far right and then horizontally feeding 4 ADCs. As such all analog signals are sampled at the same moment. The digital signals all reach their respective EP2C8 at the same time, but this is not essential as they are source synchronous signals.  Regards,  Josy

[Altera_Forum]

--- Quote Start ---  1) I'm not a Stratix expert, so I would need to study this further, but this is outside my scope. Perhaps somebody else will answer this question? 2) The DCO clocks (and data) go to the EP2C8 devices, as the EP2SGX60 didn't have enough LVDS Receivers. From the EP2C8's I have 4 wide-parallel LVCMOS buses feeding into the EP2SGX60. 3) You still didn't tell which Stratix IV device you are targeting? Although I have to repeat I'm not a Stratix expert at all. With 12 ADC devices you will need 12 * 6 or 96 LVDS inputs in total, and 12 of them need to feed into a clock input. Achieving timing closure at 1000 Mbps, using static .sdc constraints, may turn out to be difficult. And using the DPA feature in the ALTLVDS may then be a better approach.   I balanced all timing delays. On the picture the analog data is fed in from the right going left, I also fed the ADC clocks first going from the EP2SGX60 FPG to the far right and then horizontally feeding 4 ADCs. As such all analog signals are sampled at the same moment. The digital signals all reach their respective EP2C8 at the same time, but this is not essential as they are source synchronous signals.  Regards,  Josy  --- Quote End ---    Hi Josy,  1. My FPGA part is EP4SGX230KF40C4. 2. If i use ALTLVDS megafunction, my fpga doesn't support 12 ALTLVDS modules. There are toal 4 altlvds module in EP4SGX230KF40.  3. Can the DDIO decrease the speed from 1000Mbps to 500Mbps after the ADC data come into FPGA? If this is the case, the register shift will run at 500MHz in logic.   BTW, I have a thought, however, i don't know if this can be implemented. You know, i will group 3 or 4 AD9633 into a group. So can i only connect one of the group's ADCs DCO to fpga, and process them by using one ALTLVDS module as the attaced image shows. Then i can receive all 12 AD9633 by 4 altlvds modules. The key issue is if DCO connected to fpga synchronizes with other ADCs output data? If not, the logic design will lose relationship between clock and data. I can carefully route the clock trace to all ADC, and ensure their lengh to be equal. http://www.alteraforum.com/forum/attachment.php?attachmentid=13055&stc=1