using lvds

[Altera_Forum]

G´day !! 

 I´m using an ADC with differential output (LVDS). It´s a device including 8 ADCs with Serial LVDS output. Data from each ADC is serialized and provided on a seperate channel. This serial data (data rate for each serial stream is 700Mbps maximum) is read with Cyclon III. What´s the best way to do this ? I found the ALTLVDS Megafunction, but i think this block has no sense, cause of the serialization factor of 1 for each channel used in my system. But what´s the best way to read and process the sampled input data ?? Is it possible to wire this LVDS Serial data direct to a PIO ???   hope someone can help me greets !!!

[Altera_Forum]

I'm going to using Stratix IVGX deivce, and have to use column I/O LVDS pairs to receive ADC output.

[Altera_Forum]

--- Quote Start ---  Hi Josy,  1. My FPGA part is EP4SGX230KF40C4. 2. If i use ALTLVDS megafunction, my fpga doesn't support 12 ALTLVDS modules. There are toal 4 altlvds module in EP4SGX230KF40.  3. Can the DDIO decrease the speed from 1000Mbps to 500Mbps after the ADC data come into FPGA? If this is the case, the register shift will run at 500MHz in logic.   BTW, I have a thought, however, i don't know if this can be implemented. You know, i will group 3 or 4 AD9633 into a group. So can i only connect one of the group's ADCs DCO to fpga, and process them by using one ALTLVDS module as the attaced image shows. Then i can receive all 12 AD9633 by 4 altlvds modules. The key issue is if DCO connected to fpga synchronizes with other ADCs output data? If not, the logic design will lose relationship between clock and data. I can carefully route the clock trace to all ADC, and ensure their lengh to be equal.   --- Quote End ---    Hi Jerry,  I did some more study, and I believe you can have your cake and eat it :) IMHO it can work as you describe / have drawn. Almost, as you will have to feed one FCO clock instead of one DCO clock (per group of 3 aggregated ADCs). The ALTVDS PLL requires the base clock as input. https://www.alteraforum.com/forum/attachment.php?attachmentid=13057  The FCO clocks of the three ADCs in each block will run at (exactly) the same frequency, but with an unknown phase-shift. But this phase-shift doesn't matter as the DPA circuitry in the receiver datapath will select the best phase for each data signal. It could be advantageous if you can match the trace lengths per group of 3 ADCs. The four groups can have quite different trace lengths. Also don't over-strain your self with matching the lengths between signals; 50 ps is about 7 mm trace length. Although IMHO it won't matter, the DPA will select the phase of the PLL clock to sample within 1/16 of the UI (or 62.5 ps in your case) of the ideal position.  I would be careful though and also seek advice from the other Experts (FvM, Tricky, ... ?) too.  Regards, Josy

[Altera_Forum]

--- Quote Start ---  I'm going to using Stratix IVGX deivce, and have to use column I/O LVDS pairs to receive ADC output.  --- Quote End ---    Yes, column I/O LVDS pins would also be one of the solutions for our case. However, our system still use many normal I/O pins to interface other parts. So i have to group several ADC devices to save I/O pins resource.

[Altera_Forum]

--- Quote Start ---  Hi Jerry,  I did some more study, and I believe you can have your cake and eat it :) IMHO it can work as you describe / have drawn. Almost, as you will have to feed one FCO clock instead of one DCO clock (per group of 3 aggregated ADCs). The ALTVDS PLL requires the base clock as input. http://www.alteraforum.com/forum/attachment.php?attachmentid=13057&stc=1  The FCO clocks of the three ADCs in each block will run at (exactly) the same frequency, but with an unknown phase-shift. But this phase-shift doesn't matter as the DPA circuitry in the receiver datapath will select the best phase for each data signal. It could be advantageous if you can match the trace lengths per group of 3 ADCs. The four groups can have quite different trace lengths. Also don't over-strain your self with matching the lengths between signals; 50 ps is about 7 mm trace length. Although IMHO it won't matter, the DPA will select the phase of the PLL clock to sample within 1/16 of the UI (or 62.5 ps in your case) of the ideal position.  I would be careful though and also seek advice from the other Experts (FvM, Tricky, ... ?) too.  Regards, Josy  --- Quote End ---    Hi Josy,  Thanks for you reply me so quickly.  This is the first time we use serial LVDS ADC devices in our applications, our previous ADC parts are AD9218 and AD9288. So i need study more and think more before we finish hardware schematic design. Your comments make me more confident. Is it better that use DCO as clock and FCO as word edge indicator? As lvds pins are enough for my case, and each ADC's FCO may be connected to FPGA.   Furthermore, what is the skew effect among ADC devices in one group? I don't know if the convertion delay is consistent among differnet ADC devices? I don't worry about this among channels inside one ADC device.   Actually, i'm study TI's ADS52J90 datasheet during i studying AD9633 (and AD9681, which must use 2-lane, will consume more lvds lines, and pass). Question is the input BW of ADS52J90 is only 70MHz.