using memory ram in cycloneII - Intel Community

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using memory ram in cycloneII

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Hi!

What is the verilog code to tell the compiler to use the internal RAM chip?

reg[7:0] ram[1024];

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take a look at the Verilog templates in Quartus II under Edit > Insert Template

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405 Views

tnx!

is it correct?

module ram(clk,data,myaddr,myram);

input clk;

input[7:0] data;

input[9:0] myaddr;

output[7:0] myram;

reg[7:0] myram[1023:0];

always@(posedge clk)

myram[myaddr]<=data;

endmodule

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