Programmable Devices

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Programmable Devices

Discussions

Intel HLS (High Level Synthesis) compiler

Cyclone II , Fifo UART, Nios II

Unconstrained paths in timequest result in setup violation

Missing figure in documentation

MAX 10 PCI 3.0V vs 3.3V

No JTAG after AS programming on EP2C5T144

Cyclone 10 GX supporting DDR3

Fractional N PLL implimentation in IP possible on Cyclone V and max10?

clock mux, clock dividers and best clock constraints to use

Giving external input to Triple Speed Ethernet

Quartus 17 position of symbol labels different for VHDL and block diagram/schematic

Issues with PLL's in Cyclone V SoC

Questions on PCIE communication protocol implementation in RIFFA

Max10: ADC not working with .pof file

Arria V SoC HPS EMAC 1588 PTP Feature

Featured Content

AGILEX5 - HPS-first - timeout waiting for RECONFIG_COMPLETED

10M04SCU324I7G - I/O timing

SDI pinning on Agilex 5

I350 igb driver failed with error -2

Request for the Product Lifecycle Status

Re: USB Blaster selection criteria

Solution: USB Blaster Driver for Windows 11 ARM

Re: MAX10 (Select Internal Configuration mode with ERAM )