verilog code for nand flash memory

[Altera_Forum]

hi all, 

my english is not so fluent,but i really need help for my homeworks.  module nand_flash(clk, rst, done, F_IO_A, F_CLE_A, F_ALE_A, F_REN_A, F_WEN_A, F_RB_A, F_IO_B, F_CLE_B,   F_ALE_B, F_REN_B, F_WEN_B, F_RB_B);   input clk; input rst; output done; inout [7:0] F_IO_A; output F_CLE_A; output F_ALE_A; output F_REN_A; output F_WEN_A; input F_RB_A; inout [7:0] F_IO_B; output F_CLE_B; output F_ALE_B; output F_REN_B; output F_WEN_B; input F_RB_B;     always@(posedge clk) begin  if(reset==1)  begin   endmodule   the above is all what i can write  need help plz

[Altera_Forum]

This is nothing but a code outline. Why not cone back and ask for help when you've actually had a go at the problem yourself.

[Altera_Forum]

And figure it out yourself, don't just google for some code. Students need to realize that you don't learn something with google. The point of the assignment isn't to get a flash controller off the internet, but to teach you to create one.  

 Start with the data sheet for the flash chip you are using. Think in terms of implementing the timing diagrams you see there.

[Altera_Forum]

--- Quote Start ---  hi all, my english is not so fluent,but i really need help for my homeworks.  module nand_flash(clk, rst, done, F_IO_A, F_CLE_A, F_ALE_A, F_REN_A, F_WEN_A, F_RB_A, F_IO_B, F_CLE_B,   F_ALE_B, F_REN_B, F_WEN_B, F_RB_B);   input clk; input rst; output done; inout [7:0] F_IO_A; output F_CLE_A; output F_ALE_A; output F_REN_A; output F_WEN_A; input F_RB_A; inout [7:0] F_IO_B; output F_CLE_B; output F_ALE_B; output F_REN_B; output F_WEN_B; input F_RB_B;     always@(posedge clk) begin  if(reset==1)  begin   endmodule   the above is all what i can write  need help plz  --- Quote End ---   is this a joke chloe?