vhdl -division program

[Altera_Forum]

hi to all 

if anybody having coding for division please do help me

[Altera_Forum]

here is division in VHDL: 

 a <= b / c;

[Altera_Forum]

DOes the quartus supply the special circuit for division? 

What's the restriction or result fomat for a ,b and c on condition of a<=b/c?

[Altera_Forum]

he only wanted division in VHDL - he never said anything about synthesising it.

[Altera_Forum]

Aha! But I want to know if both the dividend and divider are integer, if so the result must be integer too? 

Many hardware and synthesis tools support the division implementation, and also many have special IP division module where the synthesis should be implemented.&#12288;&#65331;&#65359;&#65292;&#65353;&#65350;&#12288;&#65365;&#65363;&#65349;&#12288;&#65345;&#65308;&#65309;&#65346;&#65295;&#65347;&#65292;&#65353;&#65363;&#12288;&#65364;&#65352;&#65349;&#12288;&#65364;&#65359;&#65359;&#65356;&#12288;&#65364;&#65359;&#12288;&#65353;&#65357;&#65360;&#65356;&#65349;&#65357;&#65349;&#65358;&#65364;&#12288;&#65353;&#65358;&#12288;&#65321;&#65328;&#12288;&#65311;

[Altera_Forum]

With ieee.numeric_std, Quartus actually infers signed and unsigned dividers from HDL code, so you don't necessarily need to instantiate a divider MegaFunction. If you want multiple pipeline stages or other special features, you still need the Megafunction. With ieee.std_logic_arith, dividers are apparently only infered for the integer data type.

[Altera_Forum]

but when i use quartus it is not accepting the division(/)

[Altera_Forum]

--- Quote Start ---  quartus it is not accepting the division(/)  --- Quote End ---   It does, under the conditions I told. (Valid at least for V9.0 and later).

[Altera_Forum]

--- Quote Start ---  but when i use quartus it is not accepting the division(/)  --- Quote End ---    are you trying to divide std_logic_vectors?  you cant do that. a std_logic_vector is not a number.

[Altera_Forum]

For division between unsigned, you need "USE ieee.numeric_std.all;" in VHDL (I think)

[Altera_Forum]

if you want to do division of any significant bitwidth (>3~4 bits num and den), you need to instantiate the divider megafunction and then configure it to have several pipe stages. This will allow it to meet timing when you actually try to compile it. 

If you want some fractional bits in your answer, then you need to tack on some zeros in the numerator (similar to left shifting the number in c eg. shifted_num = num << frac_bits).

[Altera_Forum]

--- Quote Start ---  if you want to do division of any significant bitwidth (>3~4 bits num and den), you need to instantiate the divider megafunction  --- Quote End ---   Cyclone III achieves > 50 MHz for a 8:8 Bit signed and > 40 MHz for a 12:8 Bit unsigned divider (between registers). This is at least a significant bitwidth at reasonable clock frequency, I think. If you want more, you need divider internal pipelining and the alt_div MegaFunction.

[Altera_Forum]

you can try adding some extra registers and turning on register retiming, but lpm_divide seems to have significantly better performance.

[Altera_Forum]

--- Quote Start ---  you can try adding some extra registers and turning on register retiming  --- Quote End ---   Sounds like poor mans pipelining, but an interesting suggestion though. Seriously, if the infered divider doesn't achieve the intended speed, you should use an explicite instantiation.

[Altera_Forum]

--- Quote Start ---  It does, under the conditions I told. (Valid at least for V9.0 and later).  --- Quote End ---      If i use version 9 or later will it accept the division . i have not yet used version 9.

[Altera_Forum]

Divider interference works with previous Quartus versions as well, I checked V6.0 and V8.1. I guess, you ignored the other points that have been said in the above discussion.

[Altera_Forum]

Or the best solution is to redesign the algorithm so that you dont have to do the divide in the first place - stick to multiplies instead. 

 a/b = a * 1/b. Do the 1/b function on something else (like a processor) if you can.

[Altera_Forum]

--- Quote Start ---  Or the best solution is to redesign the algorithm so that you dont have to do the divide in the first place - stick to multiplies instead.  a/b = a * 1/b. Do the 1/b function on something else (like a processor) if you can.  --- Quote End ---    but 1/b also has a division then how can it accept?. or how to do it

[Altera_Forum]

--- Quote Start ---  but 1/b also has a division then how can it accept?. or how to do it  --- Quote End ---    Hence why I said take it off FPGA onto something like a processor.  Division can be done fine on an FPGA, it just eats through resources.

[Altera_Forum]

If speed is not important you could fall back on a serial divider mechanism, doing 'long division' in binary.

[Altera_Forum]

--- Quote Start ---  Sounds like poor mans pipelining, but an interesting suggestion though.  --- Quote End ---   if by poor you mean lazy, certainly. :)  it would be nice if register retiming could meet the fmax of an lpm function. i haven't found it to do so with wide multipliers (24 bit) in CIII either.