vhdl -division program

[Altera_Forum]

hi to all 

if anybody having coding for division please do help me

[Altera_Forum]

--- Quote Start ---  but 1/b also has a division then how can it accept?. or how to do it  --- Quote End ---   you can look at 'a' as an 8 bit integer, say 51 which is 00110011  say you wanted to divide by 3. we will actually multiply by 1/3 in 8 bits fractional, so 'b' is 0.010101  00110011 x 0.010101 = 000010001.0000100  51 * 0.328125 = 17.03125  the decimal point is an abstraction. anyhow, this may work for your application (maybe if 'b' only has a few possible values) and only uses a 9 bit signed multiplier. hopefully someone can double check my work, its been awhile...

[Altera_Forum]

--- Quote Start ---  it would be nice if register retiming could meet the fmax of an lpm function.  --- Quote End ---  In the meantime I checked this point, and I found, that the integrity of the divider IP isn't touched by the compiler/fitter. No available register is moved into the divider logic. I think it can be understood from the fact, that the divider inference doesn't provide the option to connect a clock, so it can't use the pipeline option.  Regarding the suggestion to replace a division by a multiply. I'm using this in two situations: - when the divisor is a constant, as discussed above - when the divisor is a signal, but can tolerate a larger latency time than the dividend. Then 1/b can be calculated by a slow serial divider and multiplied with a in a single clock cycle. If both a and b must be processed with low latency time, it doesn't work.

[Altera_Forum]

--- Quote Start ---  In the meantime I checked this point, and I found, that the integrity of the divider IP isn't touched by the compiler/fitter. No available register is moved into the divider logic. I think it can be understood from the fact, that the divider inference doesn't provide the option to connect a clock, so it can't use the pipeline option.  --- Quote End ---   i do see registers get moved into internal divider logic.  i am using Altera's signed I/O registered multiplier VHDL template as a reference (multiply changed to divide). i was using 40 bit input and outputs for this test. first run achieves 4.83 MHz (CIII -8). adding an extra input stage of input registers gets the design to 6.41 MHz. that's a 33% improvement! adding another stage of input registers does not improve performance, which is the part i found interesting. maybe worth an enhancement request.  either way the lpm_divide still wins with 2 pipeline stages somewhere in the 10 MHz range. :eek:

[Altera_Forum]

my understanding of how register retiming works is that when combination logic is surrounded by registers, the registers can be moved in order to improve timing. the divider itself doesn't have to be pipelined.

[Altera_Forum]

I verified that you are right. But interestingly, the registers are only move into the divider logic from the input side. In my first test, I had single input and output registers and added more output registers. This had no effect on the maximum operating frequency. Redundant registers from the divider input side can be used.

[Altera_Forum]

interesting that the output registers don't work.

[Altera_Forum]

--- Quote Start ---  you can look at 'a' as an 8 bit integer, say 51 which is 00110011  say you wanted to divide by 3. we will actually multiply by 1/3 in 8 bits fractional, so 'b' is 0.010101  00110011 x 0.010101 = 000010001.0000100  51 * 0.328125 = 17.03125  the decimal point is an abstraction. anyhow, this may work for your application (maybe if 'b' only has a few possible values) and only uses a 9 bit signed multiplier. hopefully someone can double check my work, its been awhile...  --- Quote End ---    Expanding on this, you could could use a lookup table to return your 1/n values and feed the output into a multiplier. Use n as the look up address, and have the table pre-calculated. This can run very very fast and wont eat up resources like a divider.  Of course, this is only viable if you have a small number of bits in the denominator. In an Arria2/stratix 4 you'll probably be fine with 16 bits or so, but memory will start to dissapear after 8 bits with smaller devices.

[Altera_Forum]

but i hav to use multiple pipeline stages then what can i do for that

[Altera_Forum]

--- Quote Start ---  but i hav to use multiple pipeline stages then what can i do for that  --- Quote End ---    How many bits are in the numerator and denominator? As I said, if you use a look up table to do the 1/n division, the pipeline is already built in to the division.

[Altera_Forum]

numerator is 10 bits of binary which i convert it into integer ,then denominator is directly i have taken as integer (i.e) 20 

 and i dont know how to use look up table because my coding is like loop for example my coding contains    xkcap0(0)=conv_std_logic_vector((conv_integer(fn(0))*conv_integer(xkcap0(0))/20...................... and so on.........  here fn(0) is of 6 bits and initially xkcap0(0) is of 10 bits which is 0 initially. here xkcap(0) is also used inside the coding .....so how to calculate data for look up table because each and every time xkcap(0) will change

[Altera_Forum]

All you need to do is work out all 1024 possible values for xkcap0/20 and put them into a ROM. Then use xkcap0 to address into the ROM and multuply the output by fn(0)