Thank you for contacting Intel community.
Have you follow MAX 10 configuration userguide? If not, please kindly refer to the userguide below:
Let me know if you need further information.
thanks a lot for you help,
after powering on, the fpga will:
- be configured by the configuring file
- after being configured , reset the whole register,
- go to implement the function
the content you mentioned above is the work in phase 1 , and what I care about is in phase 2 above,
- firstly can I use locked of the pll to reset the register of the fpga as below:
assign reset = locked ?
2. secondly , or should I construct a Resistance capacitance charging circuit to get the reset signal , and then input the reset signal to the FPGA ?
what is the best mode to reset the fpga register ?
- You can perform reset by using PLL or reset IP.
- You can also write RTL to perform reset internally when there is some problem
or you can connect the reset input to a switch
depends on your design.