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jzhao59
Beginner
389 Views

what's the reason that the fitter has error when running native phy on sx2800?

Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 HSSI_RX_CHANNEL_CLUSTER(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. 

Error(175020): The Fitter cannot place logic HSSI_RX_CHANNEL_CLUSTER that is part of L-Tile/H-Tile Transceiver Native PHY Intel Stratix 10 FPGA IP top_nphy_altera_xcvr_native_s10_htile_180_fzbjb6i in region (0, 29) to (2, 90), to which it is constrained, because there are no valid locations in the region for logic of this type. 

Info(14596): Information about the failing component(s): 

Info(175028): The HSSI_RX_CHANNEL_CLUSTER name(s): aurora_top_1|nphy_inst|nphy|nphy|g_xcvr_native_insts[0].ct2_xcvr_native_inst|inst_ct2_xcvr_channel_multi|gen_rev.ct2_xcvr_channel_inst|gen_ct1_hssi_cr2_pma_rx_dfe.inst_ct1_hssi_cr2_pma_rx_dfe~HSSI_RX_CHANNEL_CLUSTER2 

Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below: 

Info(175013): The HSSI_RX_CHANNEL_CLUSTER is constrained to the region (0, 29) to (2, 90) due to related logic 

Info(175015): The I/O pad txp[0] is constrained to the location PIN_AM42 due to: User Location Constraints (PIN_AM42) 

Info(14709): The constrained I/O pad is contained within a HSSI_TX_CHANNEL_CLUSTER, which is contained within a HSSI_DUPLEX_CHANNEL_CLUSTER, which contains this HSSI_RX_CHANNEL_CLUSTER 

 

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Deshi_Intel
Moderator
130 Views

Hi, At high level based on error message, looks like you are placing transceiver Rx channel on a transceiver Tx channel pin location. But to confirm, can you share out your Quartus design archived *.QAR file then I can help you to analyze the fitter error better ? You can also checkout below link on transceiver channel placement guideline for Stratix 10 FPGA. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an778.pdf Thanks. Regards, dlim
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