why my AD data reset my 3c120??

[Altera_Forum]

when AD data outputs connect to EP3C120, the 3C120 reset after download the sof, the signal is also can't run, quartus wondiow iprompted JTAG communication error, the message window " can't find the instance.Download a design with SRAM object File containing this instance，" 

but if the clock is below 45MHz（ＡＤ　sample clock is the same as the FPGA's clk) it's all ok, FPGA can run successfully ,and get the AD data.  Can AD data reset the FPGA,??? Thanks a lot!

[Altera_Forum]

Which hardware platform (dev kit, custom board) you're referring to?

[Altera_Forum]

I am refering a custom board, the sof can run normally in that board, 

This two boards FPGA configration is the same, I haved checked it.

[Altera_Forum]

You should consider a short between configuration and other signals. Or shorted data lines, that may cause a supply overload.

[Altera_Forum]

Thank you for you reply.  

You mean configuration and other signals maybe short in my board, or some data lines are short in my board? Is it possible that the noise of AD is too big to 3C120 run normally , espically when CLK is high.   "supply overload" is the power supply overload, Or singnal overload?

[Altera_Forum]

Hello. the problem is resloved, the power supply is real overload, the power supply of the newboard is different from the old one, the DC-DC is said to offer up to 2A current, but it can't offer so much in fact, when I cheng the power supply of 1.2V, the phenomenon isn't exist. 

 Thank you very much!!