I tried to generate using your IP file and also get the error during generation. Can you list out which setting that you wish to generate? I think maybe we need turn on one by one and determine which setting cause the error. By the way, do you try other pro version?
After playing around the setting on by one, I found the culprit is "Address width of accessible PCIe memory space".
The generation errors will occur when we set the value to 63 and 64. It will generate the example design successfully when we set the value to 62 and below.
As temporary work around, can you generate the design using "Address width of accessible PCIe memory space" set to 62 or below?
What is the IP that you using and what FPGA device?
Based on the IP file that you attached in this thread early. I am open it with Quartus 19.4 and it give me Avalon-MM Intel S10 Hard IP for PCIe.
And based on this IP, the Avalon-MM setting tab is looks like this screenshot.
It is different from your screenshot. And the parameter that I mentioned is the “Address width of accessible PCIe memory space” as highlight in yellow. You should set it to 62 or below.