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I'm trying to understand the microarchitecture details for Sapphire Rapids (and Emerald once it's released).
I'm aware of the Software Developer Manuals but they are very focused on Alderlake, which obviously doesn't have processor-processor, no AVX-512 etc.
I'm interested in core-core, processor-processor, cache latencies, local and remote memory lookups, TLB, execution units, AVX-512, cache line throughput, everything. Basically the same type of information as found in the Software Developer Manuals........ but specific to the Xeons.
There's a couple of websites which have done testing on SPR but it would be good to have definite Intel documentation.
Do any documents exist? Can anything be released?
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Hello processor77,
Thank you for posting on the Intel® communities.
We would like to inform you that we have a forum for these specific issues and products, so we are moving it to the "server-products" forum so you can get better support for this matter.
Regards,
Deivid A.
Intel Customer Support Technician
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Hi Processor77,
Thank you for posting on the Intel® community.
As you mentioned about the Software Developer Manuals for Sapphire Rapids, we request you to please help us with the link which you are referring to.
This will help us to assist you further.
Regards,
Megha
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Hi Processor77,
Thank you for posting on the Intel® community.
In continuation with the previous post, as you mentioned about the Software Developer Manuals for Sapphire Rapids, we request you to please help us with the link which you are referring to.
This will help us to assist you further.
Regards,
Megha
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Hi Processor77,
Thank you for posting on Intel community.
We have not received a reply from you , and as such, we will be closing your chat.
If you want to continue support, please reply to this email and we will reopen your chat or create a new one so that we can continue to support you.
Best Regards,
Megha k
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