cache coherence in Xeon

[ASing3]

Hi

I need to model and quantify penalty incurred when a data is there in a processor private cache(L1,L2) and some other core need to access it. I am interested in both xeon and Xeon phi processors.

I would like to know where a cache coherence unit snoops in xeon?

when processor access a location from L1 or when a req is made to L2 or when a req is made to L3.

how it is handled in directory based cache unit of xeon phi (knight landing)?

some insight about how to measure them on actual processors would be really nice.

thanks

Ajit

[idata]

Hi Ajit_ald_in,

Thank you for bringing this to our attention, let me help you on this matter.Please bear in mind that I can help with the Intel® Xeon® processor since this is my area of support.For Intel® Xeon Phi™ Processors, please address this matter at the proper /community/tech/servers support areaI will need to gather some information about your hardware configuration, please run the following utility and attach the report.https://downloadcenter.intel.com/download/25293/Intel-System-Support-Utility-for-Windows https://downloadcenter.intel.com/download/25293/Intel-System-Support-Utility-for-Windows-Thank you for your time.Allan J.

[idata]

Hi Ajit_ald_in,

I was wondering if you were able to gather the system information through the Intel® SSU utility.Regards,Allan J.