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Estimate L1, L2 cache size of Knights Landing in photo die

Sunjung_L_
Beginner
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Hello all,

I'm writing to know how to estimate or calculate L1, L2 cache size of Knights Landing in photo die

Below is the information about Knights Landing,

Die size: 683mm^2 (31.9mm x 21.4mm)
Silicon size: 14nm
Transistor: 8 billion

Is there any equation to estimate L1, L2 cache size with information? 

Thank you.

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JJK
New Contributor III
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just look up the specs on ark.intel.com ...

L1: 16 K

L2: 1 MB per core

L3: 32 MB for a 64 core machine, 34 MB  for a 68 core machine, 36 MB for a 72 core machine

Each core has 4 threads.

 

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Zhen
Beginner
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I do not think KNL has L3 cache.

L1: 32K

L2:1MB shared by 2 cores.

More info can be found from the paper KNIGHTS LANDING: SECONDGENERATION INTEL XEON PHI PRODUCT (https://www.computer.org/cms/Computer.org/ComputingNow/issues/2016/06/mmi2016020034.pdf)

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JJK
New Contributor III
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Whoops, I stand corrected: you are absolutely right.

You could consider the MCDRAM to be a L3 cache, but the MCDRAM is not low-latency memory...

 

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Sunjung_L_
Beginner
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Ops, I think my writing has confused you.

I want to know 'real' cache size (e.g. mm^2) in photo die.
So, I've written information about die size, silicon size and number of transistor of KNL.
In other words, I want to calculate the portion of real L1, L2 size in photo die(683mm^2)

If you know about this information, please let me know.

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