How many general vector registors does the MIC vpu have?

[Yuan_Y_]

From http://software.intel.com/en-us/articles/intel-xeon-phi-coprocessor-vector-microarchitecture :

"The VPU state per thread is maintained in 32 512-bit general vector registers (zmm0-zmm31), 8 16-bit mask registers (K0-K7)"

Does this mean there are 32 general vector registers per vpu or 128 general vector registers?

Thanks,

[TimP]

There are 32 program accessible zmm registers per logical thread (244 total logical threads on 61 cores).  Each 32 register set is visible only to the thread running in that context, although there are 128 per core if you count all 4 logical threads.  Each thread gets a distinct physical register associated with the same number in the code.

[Yuan_Y_]

Thanks. If I am running two threads per core, and each thread utilizes 32 vector registers, no contention for the vector registers will happen between these two threads. Is this the case?

[robert-reed]

Yes, same answer as before.  Each core has sufficient recources to supply registers for all HW threads running on that core.  That's true whether you're running two, three or four threads.  Those registers represent architectural state of the corresponding HW threads even when other threads are running on the core and so must be preserved.  The reservation station can be conceived as a step along the ALU pipeline so there's no contention between threads for allocation.

[Kaixi_H_]

I believe in the same document, it mentions each core has 128 entry of 512-bit vector register.